Programming Note - Epson 0C88832 Technical Manual

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
KCP00–KCP07: 00FF52H
KCP10: 00FF53H•D0
Sets the interrupt generation condition (interrupt
generation timing) for input port terminals K00–
K07 and K10.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading:
KCPxx is the input comparison register which
correspond to the input port Kxx. Interrupt in those
ports which have been set to "1" is generated on the
falling edge of the input and in those set to "0" on
the rising edge.
At initial reset, this register is set to "1" (falling edge).
PK00, PK01: 00FF20H•D6, D7
PK10, PK11: 00FF21H•D0, D1
Sets the input interrupt priority level. The two bits
PK00 and PK01 are the interrupt priority registers
corresponding to the interrupts for K00–K07 (K0L
and K0H). Corresponding to K10 (K1), the two bits
PK10 and PK11 perform the same function.
Table 5.4.4.2 shows the interrupt priority level
which can be set by this register.
Table 5.4.4.2 Interrupt priority level settings
PK11 PK10
PK01 PK00
1 1
1 0
0 1
0 0
At initial reset, this register is set to "0" (level 0).
EK0L, EK0H, EK1: 00FF23H•D3, D4, D5
How interrupt generation to the CPU is permitted
or prohibited.
When "1" is written: Interrupt permitted
When "0" is written: Interrupt prohibited
Reading:
The interrupt enable register EK0L corresponds to
K00–K03, EK0H to K04–K07, and EK1 to K10.
Interrupt is permitted in those series of terminals
set to "1" and prohibited in those set to "0".
At initial reset, this register is set to "0" (interrupt
prohibited).
38
Valid
Interrupt priority level
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
Valid
FK0L, FK0H, FK1: 00FF25H•D3, D4, D5
Indicates the generation state for an input interrupt.
When "1" is read:
When "0" is read:
When "1" is written: Reset factor flag
When "0" is written: Invalid
The interrupt factor flag FK0L corresponds to K00–
K03, FK0H to K04–K07, and FK1 to K10 and they
are set to "1" by the occurrence of an interrupt
generation condition.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is all reset to "0".

5.4.5 Programming note

When changing the input terminal from LOW level
to HIGH with the built-in pull-up resistor, a delay
in the waveform rise time will occur depending on
the time constant of the pull-up resistor and the
load capacitance of the terminal. It is necessary to
set an appropriate wait time for introduction of an
input port. In particular, special attention should be
paid to key scan for key matrix formation. Make
this wait time the amount of time or more calcu-
lated by the following expression.
Wait time = R x (C
IN
R : Pull up resistance Max. value
IN
C : Terminal capacitance Max. value
IN
EPSON
Interrupt factor present
Interrupt factor not present
+ load capacitance on the
IN
board) x 1.6 [sec]
E0C88832/88862 TECHNICAL MANUAL