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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
HALT status
By executing the program's HALT instruction, the
E0C88832/88862 shifts to the HALT status.
Since CPU operation stops in the HALT status,
power consumption can be reduced with only
peripheral circuit operation.
Cancellation of the HALT status is done by initial
reset or an optional interrupt request, and the CPU
restarts program execution from an exception
processing routine.
See the "E0C88 Core CPU Manual" for the HALT
status and reactivation sequence.
SLEEP status
By executing the program's SLP instruction, the
E0C88832/88862 shifts to the SLEEP status.
Since the operation of the CPU and peripheral circuits
stop completely in the SLEEP status, power consump-
tion can be reduced even more than in the HALT status.
Cancellation of the SLEEP status is done by initial
reset or an input interrupt from the input port. The
CPU reactivates after waiting 8,192/f
of oscillation stabilization time. At this time, the
CPU restarts program execution from an exception
processing routine (input interrupt routine).
Note: Since oscillation is unstable for a short time
after reactivation from the SLEEP status, the
wait time is not always 250 msec even when
using the 32.768 kHz crystal oscillator for
the OSC1 oscillation circuit.
5.14.1 Interrupt generation conditions
The interrupt factor flags that indicate the generation
of their respective interrupt factors are provided for
the previously indicated 6 systems and 15 types of
interrupts and they will be set to "1" by the genera-
tion of a factor.
Programmable timer 1 underflow
Programmable timer 0 underflow
Non matching of the K10 input and the input comparison register KCP10
Non matching of the K04–K07 inputs and the input comparison registers KCP04–KCP07
Non matching of the K00–K03 inputs and the input comparison registers KCP00–KCP03
Serial interface receiving error (in asynchronous mode)
Serial interface receiving completion
Serial interface transmitting completion
Falling edge of the stopwatch timer 100 Hz signal
Falling edge of the stopwatch timer 10 Hz signal
Falling edge of the stopwatch timer 1 Hz signal
Rising edge of the clock timer 32 Hz signal
Rising edge of the clock timer 8 Hz signal
Rising edge of the clock timer 2 Hz signal
Rising edge of the clock timer 1 Hz signal
114
In addition, interrupt enable registers with a 1 to 1
correspondence to each of the interrupt factor flags
are provided. An interrupt is enabled when "1" is
written and interrupt is disabled when "0" is written.
The CPU manages the enable/disable of interrupt
requests at the interrupt priority level. An interrupt
priority register that sets the priority level is
provided for each of the interrupts of the 6 systems
and the CPU accepts only interrupts above the level
that has been indicated with the interrupt flags (I0
and I1).
Consequently, the following three conditions are
necessary for the CPU to accept the interrupt.
(1) The interrupt factor flag has been set to "1" by
(2) The interrupt enable register corresponding to
(3) The interrupt priority register corresponding to
seconds
OSC1
The CPU initially samples the interrupt for the first
op-code fetch cycle of each instruction. Thereupon,
the CPU shifts to the exception processing when the
above mentioned conditions have been established.
See the "E0C88 Core CPU Manual" for the excep-
tion processing sequence.
5.14.2 Interrupt factor flag
Table 5.14.2.1 shows the correspondence between
the factors generating an interrupt and the inter-
rupt factor flags.
The corresponding interrupt factor flags are set to
"1" by generation of the respective interrupt factors.
The corresponding interrupt factor can be con-
firmed by reading the flags through software.
Table 5.14.2.1 Interrupt factors
Interrupt factor
EPSON
generation of an interrupt factor.
the above has been set to "1".
the above has been set to a priority level higher
than the interrupt flag (I0 and I1) setting.
FPT1
FPT0
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
FSW100
FSW10
FSW1
FTM32
FTM8
FTM2
FTM1
E0C88832/88862 TECHNICAL MANUAL
Interrupt factor flag
(00FF25 D7)
(00FF25 D6)
(00FF25 D5)
(00FF25 D4)
(00FF25 D3)
(00FF25 D2)
(00FF25 D1)
(00FF25 D0)
(00FF24 D6)
(00FF24 D5)
(00FF24 D4)
(00FF24 D3)
(00FF24 D2)
(00FF24 D1)
(00FF24 D0)
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