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S5-100U
RS Flip-Flop with Flags (set dominant)
A "1" at input I 0.0 sets flip-flop F 1.7 (signal state "1").
If the signal state at input I 0.0 changes to "0", the state of
flag F 1.7 is maintained, i.e., the signal is latched.
A "1" at input 0.1 resets the flip-flop (signal state "0"). If
the signal state at input I 0.1 changes to "0", flag F 1.7
retains signal state "0".
If both inputs have a "1" signal state, the flip-flop is set (set
dominant).
The signal state of the flag is scanned and transferred to
output Q 1.0.
STL
A
I
0.1
R
F
1.7
A
I
0.0
S
F
1.7
A
F
1.7
=
Q
1.0
EWA 4NEB 812 6120-02
Example
CSF
F 1.7
I 0.1
R
I 0.0
S
Q
Q 1.0
STEP 5 Operations
Circuit Diagram
I 0.0
I 0.1
F 1.7
LAD
F 1.7
I 0.1
R
Q 1.0
I 0.0
S
Q
8-9
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