S5-100U
Figure 6-7 shows a possible programmable controller configuration and storage of information in the
process I/O images.
Slot
CPU
Bit
7
6
5
4
3
2
Unassigned
address area
Figure 6-7. Assignment of Process Images to the I/O Modules
EWA 4NEB 812 6120-02
0
1
2
3
°
°
°
°
°
°
°
°
°
°
°
°
DE
AI
AQ
DI
DI
1
0
0
1
2
3
4
31
Unused areas
64
65
66
67
Byte
127
PII
4
27
°
°
°
°
°
°
°
°
...
°
°
°
°
DQ
DQ
PIQ
Addressing
28
29
30
31
Bit
7 6 5 4 3 2 1 0
0
1
2
3
4
27
31
Unassigned
address area
64
65
72
79
Byte
127
6-9