Page B Registers Si5344 - Silicon Laboratories Si5342 Family Reference Manual

Si5345-44-42-D-RM

14.4.9. Page B Registers Si5344

Register 0x0B44 Output Multisynth Clock to Output Driver
Reg Address Bit Field
0x0B44 3:0
0x0B44 5
Register 0x0B46
Reg Address Bit Field
0x0B46 3:0
Register 0x0B47
Reg Address Bit Field
0x0B47 4:0
Register 0x0B48 OOF Divider Clock Disables
Reg Address Bit Field
0x0B48 4:0
Register 0x0B4A Divider Clock Disables
Reg Address Bit Field
0x0B4A 4:0
Register 0x0B57-0x0B58 VCO Calcode
Reg Address Bit Field
0x0B57 7:0
0x0B58 11:8
Type Name
R/W PDIV_FRACN_CLK_DIS
R/W FRACN_CLK_DIS_PLL
Type Name
R/W LOS_CLK_DIS
Type Name
R/W OOF_CLK_DIS
Type Name
R/W OOF_DIV_CLK_DIS
Type Name
R/W N_CLK_DIS Disable digital clocks to N dividers. Must be set to 0 to
use each N divider. See also related registers 0x0A03
and 0x0A05.
Type Name
R/W VCO_RESET_CALCODE 12-bit value. Controls the VCO frequency
R/W VCO_RESET_CALCODE
Rev. 1.0
Description
Disable digital clocks to input P (IN0–3) frac-
tional dividers.
Disable digital clock to M fractional divider.
Description
Set to 0 for normal operation.
Description
Set to 0 for normal operation.
Description
Set to 0 for normal operation
Digital OOF divider clock user disable. Bits 3:0
are for IN3,2,1,0, Bit 4 is for OOF for the XAXB
input.
Description
Description
when a reset occurs.
173