Silicon Laboratories Si5342 Family Reference Manual page 105

Si5345-44-42-D-RM
Register 0x0231 P0 Factional Division Enable
Reg Address Bit Field
0x0231 3:0
0x0231 4
Register 0x0232 P1 Factional Division Enable
Reg Address Bit Field
0x0232 3:0
0x0232 4
Register 0x0233 P2 Factional Division Enable
Reg Address Bit Field
0x0233 3:0
0x0233 4
Type Setting Name
R/W P0_FRACN_MODE
R/W P0_FRAC_EN
Type Setting Name
R/W P1_FRACN_MODE
R/W P1_FRAC_EN
Type Setting Name
R/W P2_FRACN_MODE
R/W P2_FRAC_EN
Rev. 1.0
Description
P0 (IN0) input divider fractional
mode. Must be set to 0xB for proper
operation.
P0 (IN0) input divider fractional
enable
0: Integer-only division.
1: Fractional (or Integer) division.
Description
P1 (IN1) input divider fractional
mode. Must be set to 0xB for proper
operation.
P1 (IN1) input divider fractional
enable
0: Integer-only division.
1: Fractional (or Integer) division.
Description
P2 (IN2) input divider fractional
mode. Must be set to 0xB for proper
operation.
P2 (IN2) input divider fractional
enable
0: Integer-only division.
1: Fractional (or Integer) division.
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