Registers Si5344 - Silicon Laboratories Si5342 Family Reference Manual

Si5345-44-42-D-RM
14.4.3. Page 2 Registers Si5344
Register 0x0202–0x0205 XAXB Frequency Adjust
Reg Address Bit Field
0x0202 7:0
0x0203 15:8
0x0204 23:16
0x0205 31:24
The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The
XAXB_FREQ_OFFSET word is used to adjust this frequency reference with high resolution. ClockBuilder Pro
calculates the correct values for these registers.
Register 0x0206 Pre-scale Reference Divide Ratio
Reg Address Bit Field
0x0206 1:0
0 = pre-scale value 1

1 = pre-scale value 2

2 = pre-scale value 4

3 = pre-scale value 8

This can only be used with external clock sources, not crystals.
Register 0x0208-0x020D P0 Divider Numerator
Reg Address Bit Field
0x0208 7:0
0x0209 15:8
0x020A 23:16
0x020B 31:24
0x020C 39:32
0x020D 47:40
This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, "Si5342
DSPLL and Multisynth System Flow Diagram," on page 11. ClockBuilder Pro calculates the correct values for the
P-dividers.
150
Type Name
R/W XAXB_FREQ_OFFSET
R/W XAXB_FREQ_OFFSET
R/W XAXB_FREQ_OFFSET
R/W XAXB_FREQ_OFFSET
Type Name
R/W PXAXB
Type Name
R/W P0_NUM
R/W P0_NUM
R/W P0_NUM
R/W P0_NUM
R/W P0_NUM
R/W P0_NUM
Rev. 1.0
Description
32 bit offset adjustment
Description
Sets the divider for the input on XAXB
Description
48-bit Integer Number