Silicon Laboratories Si5342 Family Reference Manual page 118

Si5345-44-42-D-RM
Register 0x052A Input Clock Select
Reg Address Bit Field
0x052A 0
0x052A 2:1
Input clock selection for manual register based and pin controlled clock selection. Note: when ZDM_EN (0x0487,
bit 0) and IN_SEL_REGCTRL are both high, IN_SEL does not do anything and the clock selection is pin controlled.
When IN_SEL_REGCTRL is low, IN_SEL does not do anything and the clock selection is pin controlled.
Register 0x052B Fast Lock Control
Reg Address Bit Field
0x052B 0
0x052B 1
When in fast lock, the fast lock loop BW can be automatically used.
Register 0x052C Holdover Exit Control
Reg Address Bit Field
0x052C 0
0x052C 3
0x052C 4
0x052C 7:5
118
Type Name
R/W IN_SEL_REGCTRL
R/W IN_SEL
Type Name
R/W FASTLOCK_AUTO_EN
R/W FASTLOCK_MAN
Type Setting Name
R/W HOLD_EN
R/W HOLD_RAMP_BYP
R/W HOLDEXIT_BW_SEL1
R/W RAMP_STEP_INTERVAL
Rev. 1.0
Description
0 for pin controlled clock selection
1 for register controlled clock selection
0 for IN0, 1 for IN1,
2 for IN2, 3 for IN3 (or FB_IN)
Description
Applies only when
FASTLOCK_MAN = 0 (see below):
0 to disable auto fast lock when the
DSPLL is out of lock.
1 to enable auto fast lock.
0 for normal operation (see above)
1 to force fast lock
Description
Holdover enable
0: Holdover Disabled
1: Holdover Enabled (default)
HOLD_RAMP_BYP
Holdover Exit Bandwidth select. Selects the exit
bandwidth from Holdover when ramped exit is
disabled (HOLD_RAMP_BYP = 1).
0: Exit Holdover using Holdover Exit or Fastlock
bandwidths (default). See HOLDEXIT_BW_-
SEL0 (0x059B[6]) for additional information.
1: Exit Holdover using the Normal loop band-
width
Time Interval of the frequency ramp steps when
ramping between inputs or when exiting hold-
over. Calculated by CBPro based on selection.