Silicon Laboratories Si5342 Family Reference Manual page 162

Si5345-44-42-D-RM
Register 0x0515-0x051B M Divider Numerator, 56-bits
Reg Address Bit Field
0x0515
0x0516 15:8
0x0517 23:16
0x0518 31:24
0x0519 39:32
0x051A 47:40
0x051B 55:48
Register 0x051C-0x051F M Divider Denominator, 32-bits
Reg Address Bit Field
0x051C 7:0
0x051E 15:8
0x051E 23:16
0x051F 31:24
The loop M divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into
these registers.
Register 0x0520 M Divider Update Bit
Reg Address Bit Field
0x0520 0
Register 0x0521 DSPLL B M Divider Fractional Enable
Reg Address Bit Field
0x0521 3:0
0x0521 4
0x0521 5
162
Type
7:0 R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
Type
R/W M_UPDATE
Type Setting Name
R/W M_FRAC_MODE_PLLB M feedback divider fractional mode.
R/W M_FRAC_EN_PLLB
R/W Reserved
Name
M_NUM 56-bit Number
M_NUM
M_NUM
M_NUM
M_NUM
M_NUM
M_NUM
Name
M_DEN 32-bit Number
M_DEN
M_DEN
M_DEN
Name
Set this bit to update the M divider.
Must be set to 0xB for proper operation.
M feedback divider fractional enable.
0: Integer-only division
1: Fractional (or integer) division - Required
for DCO operation.
Must be set to 1 for DSPLL B
Rev. 1.0
Description
Description
Description
Description