Silicon Laboratories Si5342 Family Reference Manual page 122

Si5345-44-42-D-RM
Register 0x053D
Reg Address Bit Field
0x053D 4:0
Register 0x053E
Reg Address Bit Field
0x053E 4:0
Register 0x053F
Reg Address Bit Field
0x053F 1
0x053F 2
Register 0x0588 Hitless Switching Length
Reg Address Bit Field
0x0588 3:0
Register 0x0589-0x058A PFD Enable Delay
Reg Address Bit Field
0x0589 7:0
0x058A 12:8
Register 0x059B Holdover Exit
Reg Address Bit Field
0x059B 6
122
Type Name
R/W HSW_COARSE_PM_LEN
Type Name
R/W HSW_COARSE_PM_DLY
Type Name
R/O HOLD_HIST_VALID
R/O FASTLOCK_STATUS
Type Setting Name
R/W HSW_FINE_PM_LEN
Type Setting Name
R/W CAP_SHORT_DELAY
R/W CAP_SHORT_DELAY
Type Setting Name
R/W HOLDEXIT_BW_SEL0
Rev. 1.0
Description
Set by CBPro.
Description
Set by CBPro.
Description
1 = there is enough historical fre-
quency data collected for valid
holdover.
1 = PLL is in Fast Lock operation
Description
Set by CBPro.
Description
Set by CBPro.
Description
Set by CBPro.
See HOLDEXIT_BW_SEL1