Radyne DMD15 Installation And Operation Manual page 132

DMD15/DMD15L IBS/IDR Satellite Modem
ES Baud
<1>
ES Data Bits
<1>
IDR Overhead Type
<1>
FM Orderwire Mode
<1>
Time Mark Transfer
Pattern Length
<1>
Eb/No Threshold
<2> Reacquisition Sweep
Boundary
<3> Reserved
<1> TPC Deintereleaver
<1> Control Mode
<1> Revision Number
<1> Alarm 1
<1> Alarm 2
<1> Alarm 3
TM051 - Rev. 5.8
0 = 7 Bits. 1 = 8 Bits
0 = 32K Voice. 1 = 64K Data
0 = Disable, 1 = Enable, 2 = FM Only
Unsigned Binary (4 to 16) Inclusively
Unsigned Binary Value, 0-99, Implied Decimal Point
0.0 - 9.9 dB
Unsigned binary value Sweep limits. Max of +/- 32000 Hz in 1
Hz steps 0 – 32000
Reserved
0=Disable, 1=Enable
Status Bytes
0 = Front Panel. 1 = Terminal, 2 = Computer
Decimal point implied
Bit 0 = Receive processor fault. 1 = Fail
Bit 1 = Carrier Loss. 0 = pass. 1 = Fail
Bit 2 = Multiframe Sync Loss 0 = pass. 1 = Fail
Bit 3 = Frame Sync Loss 0 = pass. 1 = Fail
Bit 4 = IBS BER Alarm 0 = pass. 1 = Fail
Bit 5 = Satellite AIS 0 = pass. 1 = Fail
Bit 6 = Rx Data Activity. 1 = Activity
Bit 7 = RX AGC Level. 0 = Pass, 1 = Fail
Bit 0 = Buffer underflow. 0 = OK. 1 = Underflow
Bit 1 = Buffer overflow. 0 = OK. 1 = Overflow
Bit 2 = Buffer under 10%. 1 = Under 10%
Bit 3 = Buffer over 90%. 1 = Over 90%
Bit 4 = RS Decoder Lock Fault. 1 = Fail
Bit 5 = RS De-Interleaver Fault. 1 = Fail
Bit 6 = RS Decoder Uncorrectable Word. 1 = Fail
Bit 7 = Summary Fault. 1 = Fail
Bit 0 = IF synthesizer lock detect. 1 = Lock
Bit 1 = Rx Oversample PLL lock detect. 1 = Lock
Bit 2 = Buffer clock PLL lock detect. 1 = Lock
Bit 3 = Viterbi decoder lock. 1 = Lock
Bit 4 = Sequential decoder lock. 1 = Lock
Bit 5 = Rx 2047 test pattern lock. 1 = Lock
Bit 6 = External reference PLL lock. 1 = Lock
Bit 7 = IDR 96K PLL Lock. 1 = Lock
User Interfaces
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