Multiple Core Special Considerations; Dts Domain For Dual-Core Intel Xeon Processor 5100 Series - Intel 5100 Series Instruction Manual

Thermal/Mechanical Reference Design
2.2.4

Multiple Core Special Considerations

2.2.4.1 Multiple Digital Thermal Sensor Operation
When Intel designers integrate multiple Digital Thermal Sensors onto a processor to
monitor multiple temperature regions, such as multiple cores, the only temperature of
concern to the external cooling system is the single hottest value for the entire
processor.
To simplify the process of determining the hottest location, the PECI interface to the
Digital Thermal Sensors introduces the concept of domain.
illustration of the DTS domain for Dual-Core Intel Xeon Processor 5100 Series. The
Dual-Core Intel Xeon Processor 5100 Series contains two cores, both cores are in one
domain with one Digital Thermal Sensor per core. Some multiple core processors have
a single domain, other processors will have multiple domains. Each domain receives all
temperature sensor values on the processor within that domain, and provides the
current hottest value for that domain when polled by an external PECI device such as a
thermal management system. The BIOS will be responsible for detecting the
proper processor type and providing the number of domains to the thermal
management system.
Figure 2-2.

DTS Domain for Dual-Core Intel Xeon Processor 5100 Series

2.2.4.2 Thermal Monitor for Multiple Core Products
The thermal management for multiple core products have only one T
processor. If the DTS temperature from any domain within the processor is greater
than or equal to T
temperature as specified by the thermal profile. See
T
CONTROL
Dual-Core Intel® Xeon® Processor 5100 Series Thermal/Mechanical Design Guide
Fan Speed Controller Fan Speed Controller Fan Speed Controller
Socket 0 Socket 0
Domain=0 Domain=0
Core_1 Core_1
Core_2 Core_2
DTS_1 DTS_1
DTS_2 DTS_2
Tcontrol for Tcontrol for
Processor 0 Processor 0
, the processor case temperature must remain at or below the
CONTROL
.
Figure 2-2
PECI Host PECI Host PECI Host
Socket 1 Socket 1
Domain=0 Domain=0
Core_1 Core_1
DTS_1 DTS_1
Tcontrol for Tcontrol for
Processor 1 Processor 1
Section 2.2.6
provides an
Core_2 Core_2
DTS_2 DTS_2
value per
CONTROL
for information on
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