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5.7
Configuring the Talon System Using the Configuration Panel (continued)
5.7.3
Parameter
<user entry> and
Bandwidth
unit of
measurement
Decimation
<user entry>
Downconversion
checkbox
Input Source
channel
Center
<user entry> MHz
Frequency
Gate/Trigger
a
Gate
Mode
Trigger
Gate/Trigger
Positive
Polarity
Negative
Internal
b
Sync Source
External
A/D Sampling
xxx.x MHz
Rate
Disk Data Rate
xxx.x MB/s
a. If you select external triggering, an external LVTTL trigger signal must be connected to the system. If an ex-
ternal LVTTL trigger signal is not connected to the system, false triggers can occur.
b. See
Section 5.7
for sync guidelines.
Rev.: 1.0
Configuring Input Channel Parameters (continued)
Table 5−2: Input Channel Parameters
Selection
To enter bandwidth, click the Bandwidth radio button and enter
your desired bandwidth. In ADC mode (no downconversion), this
bandwidth is the Nyquist bandwidth. Nyquist bandwidth = fs / (2 x
decimation). In DDC mode, this bandwidth is the usable
bandwidth, using the 80% DDC filter. Usable bandwidth = 80% x fs
/ decimation.
To enter decimation instead of bandwidth, click the Decimation
radio button and enter your desired decimation. See the bandwidth
description (above) for the relationship between bandwidth and
decimation.
Click the box to select or deselect downconversion. Your selection
determines whether you will be configuring ADC or DDC
parameters: unchecked allows ADC configuration; checked allows
DDC configuration.
This selection is only available for DDC configuration. You can
select any of the available ADCs as the input source.
This parameter is only available for DDC configuration. It sets the
Local Oscillator (NCO) frequency which translates that frequency in
the ADC sampled signal down to 0 Hz. Also known
as the tuning frequency.
The ADC/DDC delivers samples only when the logic level of the
Gate/Trigger signal is true and stops delivering samples when
false. The Gate/Trigger signal is accepted on the multi−pin digital
connector on the 786xx panel.
The ADC/DDC delivers samples when the rising or falling edge of
the Gate/Trigger signal occurs and stops delivering samples at the
end of the Record Length. The Gate/Trigger signal is accepted on
the multi−pin digital connector on the 786xx panel.
In Gate mode, the ADC/DDC delivers samples when the logic level
of the Gate/Trigger signal is 1. In Trigger Mode, the ADC/DDC
starts delivering samples at the rising (positive−going) edge of the
Gate/Trigger signal.
In Gate mode, the ADC/DDC delivers samples when the logic level
of the Gate/Trigger signal is 0. In Trigger Mode, the ADC/DDC
starts delivering samples at the falling (negative−going) edge of the
Gate/Trigger signal.
Uses the internal VCXO (voltage−controlled crystal oscillator).
Uses the externally supplied clock to the CLK SSMC connector.
Reports the calculated sampling rate of the ADC based on the
Clock Source, Clock Frequency, and Clock Divider. (See
5−1.)
Reports the rate at which this channel will record data to disk.
Talon RTX 2767 Operating Manual
Description
Table
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