Clock And Data Signals - IBM 5170 Technical Reference

Clock and Data Signals
The keyboard and system communicate over the 'clock' and
,data' lines. The source of each of these lines is an
open-collector device on the keyboard that allows either the ~
keyboard or the system to force a line to a negative level. When
no communication is occurring, both the 'clock' and 'data' lines
are at a positive level.
Data transmissions to and from the keyboard consist of ll-bit
data streams that are sent serially over the serial data line. The
following figure shows the structure of the data stream.
Bit Function
1st bit
o
start bit
2nd bit Data bit 0 (least-significant)
3rd bit Data bit 1
4th bit Data bit 2
5th bit Data bit 3
6th bit Data bit 4
7th bit Data bit 5
8th bit Data bit 6
9th bit Data bit 7 (most-significant)
10th bit Parity bit (odd parity)
11th bit Stop bit
Transmission Data Stream
The parity bit is either 1 or 0, and the eight data bits, plus the
parity bit, always have an odd number.
When the system sends data to the keyboard, it forces the' data'
line to a negative level and allows the 'clock' line to go to a
positive level.
When the keyboard sends data to, or receives data from the
system, it generates the 'clock' signal to time the data. The
system can prevent the keyboard from sending data by forcing the
I
,clocdk' linehto a negative level; the' data' line may go high or ,..-.....,
ow uring t is time.
During the BAT, the keyboard allows the 'clock' and 'data'
lines to go to a positive level.
4-14 Keyboard