IBM 5170 Technical Reference page 47

control the system address, data, and control lines (a condition
known as tri-state). After '-MASTER' is low, the I/O
microprocessor must wait one system clock period before driving
the address and data lines, and two clock periods before issuing a
Read and Write command. If this signal is held low for more than
15 microseconds, system memory may be lost because of a lack of
refresh.
-MEM CS16
(I)
'-MEM 16 Chip Select' signals the system board if the present
data transfer is a 1 wait-state, 16-bit, memory cycle. It must be
derived from the decode of LA17 through LA23. '-MEM CS16'
should be driven with an open collector or tri-state driver capable
of sinking 20 rnA.
-I/O CS16
(I)
,-I/O 16 bit Chip Select' signals the system board that the
present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is
derived from an address decode. '-I/O CS16' is active low and
should be driven with an open collector or tri-state driver capable
of sinking 20 rnA.
OSC (0)
'Oscillator' (OSC) is a high-speed clock with a 70-nanosecond
period (14.31818 MHz). This signal is not synchronous with the
system clock. It has a 50% duty cycle.
OWS (I)
The' Zero Wait State' (OWS) signal tells the microprocessor that
it can complete the present bus cycle without inserting any
~
additional wait cycles. In order to run a memory cycle to a 16-bit
device without wait cycles,
'ows'
is derived from an address
decode gated with a Read or Write command. In order to run a
memory cycle to an 8-bit device with a minimum of two wait
states,
'ows'
should be driven active one system clock after the
August 24, 1984 System Board 1-27