IBM 5170 Technical Reference page 69

Status Register B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Set-A 0 updates the cycle normally by
advancing the counts at one-per-second. A 1
aborts any update cycle in progress and the
program can initialize the 14 time-bytes without
any further updates occurring until a 0 is written
to this bit.
Periodic Interrupt Enable (PIE)-This bit is a
read/write bit that allows an interrupt to occur at
a rate specified by the rate and divider bits in
register A. A 1 enables an interrupt, and a 0
disables it. The system initializes this bit to O.
Alarm Interrupt Enable (AIE)-A 1 enables the
alarm interrupt, and a
0
disables it. The system
initializes this bit to O.
Update-Ended Interrupt Enabled (UIE)-A 1
enables the update-ended interrupt, and a 0
disables it. The system initializes this bit to O.
Square Wave Enabled (SQWE)-A 1 enables the
the square-wave frequency as set by the rate
selection bits in register A, and a 0 disables the
square wave. The system initializes this bit to O.
Date Mode (DM)-This bit indicates whether
the time and date calendar updates are to use
binary or binary coded decimal (BCD) formats.
A 1 indicates binary, and a 0 indicates BCD. The
system initializes this bit to O.
24/12-This bit establishes whether the hours
byte is in the 24-hour or 12-hour mode. A 1
indicates the 24-hour, mode and a 0 indicates the
12-hour mode. The system initializes this bit to
1.
System Board 1-47