IBM 5170 Technical Reference page 51

Mask Off Write to I/O address hex 070, with data bit 7
equal to a logic 1
Note: At the end of POST, the system sets the NMI mask on
(NMI enabled).
The following is a description of the Math Coprocessor controls.
OFO An 8-bit Out command to port FO will clear the latched
Math Coprocessor busy signal. ' Busy' will be latched if
the coprocessor asserts its error signal while it is busy. The
data output should be zero.
OFI An 8-bit Out command to port FI will reset the Math
Coprocessor. The data output should be zero.
I/O address hex 080 is used as a diagnostic-checkpoint port or
register. This port corresponds to a read/write register in the
DMA page register (74LS6I2).
The '-I/O channel check signal' (-I/O CH CK) is used to report
uncorrectable errors on RAM adapters on the I/O channel. This
~,
check will create a non-mask able interrupt (NMI) if enabled (see
the figure, "I/O Address Map," for enable control). At
power-on time, the NMI is masked off and check is disabled.
Before check or NMI is enabled, the following steps should be
taken.
1. Write data in all I/O RAM-adapter memory locations; this
will establish good parity at all locations.
2. Enable I/O channel check.
3. Enable NMI.
Note: All three of these functions are performed by POST.
When a check occurs, an interrupt (NMI) will result. Check the
status bits to determine the source of the NMI (see the figure,
"I/O Address Map"). To determine the location of the failing
adapter, write to any memory location within a given adapter. If
the parity check was from that adapter, '-I/O CH CK' will be
inactive.
System Board 1-29