IBM 5170 Technical Reference page 33

programmed, data bits D7 through D 1 should contain the
high-order seven address bits (A23 through A17) of the desired
memory space. Data bit DO of the page registers for channels 5
through 7 is not used in the generation of the DMA memory
address.
~
After power-up time, all internal locations, especially the mode
registers, should be loaded with some valid value. This should be
done even if some channels are unused.
110 Channel
The I/O channel supports:
• I/O address space hex 100 to hex 3FF
• 24-bit memory addresses (16Mb)
• Selection of data accesses (either 8- or 16-bit)
• Interrupts
• DMA channels
• I/O wait-state generation
• Open-bus structure (allowing multiple microprocessors to
share the system's resources, including memory)
• Refresh of system memory from channel microprocessors.
The following figure shows the location and the numbering of the
I/O channel connectors. These connectors consist of eight
62-pin and six 36-pin edge connector sockets.
Note: In two positions on the I/O channel, the 36-pin
connector is not present. These positions can support only
62-pin I/O bus adapters.
System Board 1-1 S