IBM 5170 Technical Reference page 385

• PUSH SP pushes the current stack pointer. The
microprocessor used in the IBM Personal Computer and the
IBM Personal Computer XT pushes the new stack pointer.
• Single step interrupt (when TF
=
1) does not occur on the
interrupt instruction (OP code hex CC,CD). The
microprocessor in the IBM Personal Computer and the IBM
Personal Computer XT does interrupt on the INT instruction.
• The divide error exception (interrupt
0)
pushes the CS:IP of
the instruction, causing the exception. The IBM Personal
Computer and the IBM Personal Computer XT push the
CS:IP following the instruction, causing the exception.
• Shift counts are masked to 5 bits. Shift counts greater than 31
are treated mod 32, that is, a shift count of 36 shifts the
operand 4 places.
Assembler language programs should perform allIiO operations
through ROM BIOS or DOS function calls.
• Program interrupts are used for access to these functions.
r"\
This practice removes the absolute addressing from the
program. Only the interrupt number is required.
• The math coprocessor detects six different exception
conditions that can occur during instruction execution. If the
appropriate exception mask within the coprocessor is not set,
the coprocessor sets its error signal. This error signal
generates a hardware interrupt (interrupt 13) and causes the
I
BUSY
I
signal to the coprocessor to be held in the busy
state. The
I
BUSY
I
signal may be cleared by an 8-bit 1/0
Write command to address hex FO with DO through D7 equal
toO.
The power-on-self test code in the system ROM enables
hardware interrupt 13 and sets up its vector to point to a
routine in ROM. The ROM routine clears the
I
BUSY
I
signal's latch and then transfers control to the address pointed
to by the NMI interrupt vector. This allows code written for
any IBM Personal Computer to work on an IBM Personal
Computer AT. The NMI interrupt handler should read the
coprocessor's status to determine if the NMI was caused by
Compatibility 9-7