IBM 5170 Technical Reference page 40

110 Channel Signal Description
The following is a description of the system board's
I/O
channel
signals. All signal lines are TTL-compatible. I/O adapters should
be designed with a maximum of two low-power Shottky (LS)
loads per line.
SAO through SA19
(I/O)
Address bits 0 through 19 are used to address memory and I/O
devices within the system. These 20 address lines, in addition to
LA17 through LA23, allow access of up to 16Mb of memory.
SAO through SA19 are gated on the system bus when 'BALE' is
high and are latched on the falling edge of 'BALE.' These
signals are generated by the microprocessor or DMA Controller.
They also may be driven by other microprocessors or DMA
controllers that reside on the
I/O
channel.
LA17 through LA23
(I/O)
These signals (unlatched) are used to address memory and I/O
devices within the system. They give the system up to 16Mb of
addressability. These signals are valid when' BALE' is high.
LA17 through LA23 are not latched during microprocessor cycles
and therefore do not stay valid for the whole cycle. Their purpose
is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling
edge of 'BALE.' These signals also may be driven by other
microprocessors or DMA controllers that reside on the I/O
channel.
eLK (0)
This is the 6-MHz system clock.
It
is a synchronous
microprocessor cycle clock with a cycle time of 167 nanoseconds.
The clock has a 50% duty cycle. This signal should only be used
~
for synchronization.
It
is not intended for uses requiring a fixed
frequency.
1-22 System Board