System Performance - IBM 5170 Technical Reference

System Performance
The 80286 Microprocessor operates at 6 MHz, which results in a
clock cycle time of 167 nanoseconds.
A bus cycle requires three clock cycles (which includes 1 wait
state) so that a 500-nanosecond, 16-bit, microprocessor cycle
time is achieved. 8-bit bus operations to 8-bit devices take 6
clock cycles (which include 4 wait states), resulting in a
lOOO-nanosecond microprocessor cycle. 16-bit bus operations to
8-bit devices take 12 clock cycles (which include 10 I/O wait
states) resulting in a 2000 nanosecond microprocessor cycle.
The refresh controller operates at 6 MHz. Each refresh cycle
requires 5 clock cycles to refresh all of the system's dynamic
memory; 256 refresh cycles are required every 4 milliseconds.
The following formula determines the percent of bandwidth used
for refresh.
%
Bandwidth used
for Refresh
5 cycles X 256 1280
5.3%
4 ms/167 ns 24000
The DMA controller operates at 3 MHz, which results in a clock
cycle time of 333 nanoseconds. All DMA data-transfer bus
cycles are five clock cycles or 1.66 microseconds. Cycles spent in
the transfer of bus control are not included.
DMA channels 0, 1, 2, and 3 are used for 8-bit data transfers, and
channels 5, 6, and 7 process 16-bit transfers. Channel 4 is used
to cascade channels 0 through 3 to the microprocessor.
The following figure is a system memory map.
System
Board 1-7