IBM 5170 Technical Reference page 43

-SMEMR (0) -MEMR (I/O)
These signals instruct the memory devices to drive data onto the
data bus. '-SMEMR' is active only when the memory decode is
within the low 1Mb of memory space. '-MEMR' is active on all
memory read cycles. '-MEMR' may be driven by any
microprocessor or DMA controller in the system. '-SMEMR
I
is
derived from' -MEMR' and the decode of the low 1Mb of
memory. When a microprocessor on the I/O channel wishes to
drive '-MEMR', it must have the address lines valid on the bus
for one system clock period before driving '-MEMR' active.
Both signals are active LOW.
-SMEMW (0) -MEMW (I/O)
These signals instruct the memory devices to store the data
present on the data bus. '-SMEMW' is active only when the
memory decode is within the low 1Mb of the memory space.
'-MEMW' is active on all memory read cycles. '-MEMW' may
be driven by any microprocessor or DMA controller in the
system.
I
-SMEMW' is derived from
I
-MEMW
I
and the decode
~
of the low 1Mb of memory. When a microprocessor on the I/O
channel wishes to drive '-MEMW', it must have the address lines
valid on the bus for one system clock period before driving
'-MEMW' active. Both signals are active low.
DRQO-DRQ3 and DRQ5-DRQ7
(I)
DMA Requests 0 through 3 and 5 through 7 are asynchronous
channel requests used by peripheral devices and the
II
0 channel
microprocessors to gain DMA service (or control of the system).
They are prioritized, with 'DRQO' having the highest priority and
I
DRQ7' having the lowest. A request is generated by bringing a
DRQ line to an active level. A DRQ line must be held high until
the corresponding 'DMA Request Acknowledge' (DACK) line
goes active. 'DRQO' through 'DRQ3' will perform 8-bit
~
DMA transfers;
I
DRQ5
I
through 'DRQ7' will perform 16-bit
transfers. ' DRQ4' is used on the system board and is not
available on the
II
0 channel.
System Board 1-25