IBM 5170 Technical Reference page 44

-DACKO
to
-DACK3 and -DACK5
to
-DACK7 (0)
-DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge
DMA requests (DRQO through DRQ7). They are active low.
AEN (0)
, Address Enable' is used to degate the microprocessor and other
devices from the I/O channel to allow DMA transfers to take
place. When this line is active, the DMA controller has control of
the address bus, the data-bus Read command lines (memory and
I/O), and the Write command lines (memory and I/O).
-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by
a microprocessor on the I/O channel.
T/C (0)
'Terminal Count' provides a pulse when the terminal count for
any DMA channel is reached.
SBHE (I/O)
'Bus High Enable' (system) indicates a transfer of data on the
upper byte of the data bus, SD8 through SDI5. Sixteen-bit
devices use 'SBHE' to condition data bus buffers tied to SD8
through SD 15.
-MASTER (I)
This signal is used with a DRQ line to gain control of the system.
A processor or DMA controller on the
I/O
channel may issue a
~
DRQ to a DMA channel in cascade mode and receive a
'-DACK'. Upon receiving the '-DACK', an I/O
microprocessor may pull '-MASTER' low, which will allow it to
1-26 System Board