IBM 5170 Technical Reference page 31

16-bit system memory. Each channel can transfer data
throughout the 16-megabyte system-address space in 64Kb
blocks.
DMA controller 2 contains channels 4 through 7. Channel 4 is
used to cascade channels 0 through 3 to the microprocessor.
1""""""'\
Channels 5, 6, and 7 support 16-bit data transfers between 16-bit
I/O adapters and 16-bit system memory. These DMA channels
can transfer data throughout the 16-megabyte system-address
space in 128Kb blocks. Channels 5, 6, and 7 cannot transfer data
on odd byte boundaries.
The following figure shows the addresses for the page register.
Page Register
I/O Hex Address
DMA
Channel 0
0087
DMA
Channel
1
0083
DMA
Channel
2 0081
DMA
Channel
3 0082
DMA
Channel
5
0086
DMA
Channel
6 0089
DMA
Channel
7 008A
Refresh
008F
Page Register Addresses
The following figures show address generation for the DMA
channels.
Source
8237A-5
Address
A15<---------->AO
Address Generation for DMA Channels 3 through 0
Note: The addressing signal, 'byte high enable' (BHE), is
generated by inverting address line AO.
Source
8237A-5
Address
A16<---------->A1
Address Generation for DMA Channels 7 through 5
Note: The addressing signals, 'BHE' and ''AO', are forced to
a logic O.
System Board 1-13