I/O Channel - IBM 5170 Technical Reference

RESET DRV (0)
I
Reset drive
I
is used to reset or initialize system logic at
power-up time or during a low line-voltage outage. This signal is
active high.
SDO through SD15 (I/O)
These signals provide bus bits 0 through 15 for the
microprocessor, memory, and I/O devices. DO is the
least-significant bit and D15 is the most-significant bit. AIl8-bit
devices on the I/O channel should use DO through D7 for
communications to the microprocessor. The 16-bit devices
will
use DO through D15. To support 8-bit devices, the data on D8
through D15 will be gated to DO through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit
devices will be converted to two 8-bit transfers.
BALE (0) (buffered)
~
I
Address latch enable
I
is provided by the 82288 Bus Controller
and is used on the system board to latch valid addresses and
memory decodes from the microprocessor. It is available to the
I/O
channel as an indicator of a valid microprocessor or DMA
address (when used with
I
AEN
I ) .
Microprocessor addresses
SAO through SA 19 are latched with the falling edge of
I
BALE.
I
'BALE' is forced high during DMA cycles.
-I/O CH CK (I)
'-I/O
channel check' provides the system board with parity
(error) information about memory or devices on the
I/O
channel.
When this signal is active, it indicates an uncorrectable system
error.
System Board 1-23