Waveforms; Figure 23. Non-Burst Read And Write Transactions Without Wait States; Figure 24. Burst Read And Write Transaction Without Wait States; Figure 25. Burst Write Transaction With 2, 1, 1, 1 Wait States - Intel 80960MC Manual
Embedded 32-bit microprocessor
with integrated floating-point unit and memory management unit
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80960MC
4.0
WAVEFORMS
The following figures present waveforms for various transactions on the 80960MC'S local bus:
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Figure 23, Non-Burst Read and Write Transactions Without Wait States (pg. 30)
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Figure 24, Burst Read and Write Transaction Without Wait States (pg. 31)
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Figure 25, Burst Write Transaction with 2, 1, 1, 1 Wait States (pg. 32)
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Figure 26, Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word
Boundary (1, 0, 0, 0 Wait States) (pg. 33)
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Figure 27, Interrupt Acknowledge Transaction (pg. 34)
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Figure 28, Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) (pg. 35)
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 23. Non-Burst Read and Write Transactions Without Wait States
30
T
T
T
a
d
r
T
T
T
a
d
r
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