Motherboard Layout Rules For Non-Agtl/Agtl+ (Cmos) Signals; Table 11. Routing Guidelines For Non-Agtl/Non-Agtl+ Signals - Intel 815 Design Manual

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5.2.1.1

Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals

Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals

Signal
A20M#
FERR#
FLUSH#
IERR#
IGNNE#
INIT#
LINT[0] (INTR)
LINT[1] (NMI)
PICD[1:0]
PREQ#
PWRGOOD
SLP#
SMI#
STPCLK
THERMTRIP#
Route these signals on any layer or combination of layers.
NOTE:
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Intel 815 Chipset Platform Design Guide
Trace Width Spacing to Other Traces
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
5 mils 10 mils
System Bus Design Guidelines
Trace Length
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
1" to 9"
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