Serial Port Mode 0 Timings - Intel 80C186EC Manual

80C186EC 188EC 80L186EC 188EC
Relative Timings (80C186EC-25 20 13 80L186EC-16 13)
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active This is not directly measureable by the user For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the T
modules
4 See INTA Cycle Waveforms for definition
5 To guarantee interrupt is not spurious
Serial Port Mode 0 Timings (80C186EC-25 20 13 80L186EC-16 13)
Symbol
RELATIVE TIMINGS
T TXD Clock Period
XLXL
T TXD Clock Low to Clock High (N
XLXH
T TXD Clock Low to Clock High (N
XLXH
T TXD Clock High to Clock Low (N
XHXL
T TXD Clock High to Clock Low (N
XHXL
T RXD Output Data Setup to TXD
QVXH
Clock High (N
T RXD Output Data Setup to TXD
QVXH
Clock High (N
T RXD Output Data Hold after TXD
XHQX
Clock High (N
T RXD Output Data Hold after TXD
XHQX
Clock High (N
T RXD Output Data Float after Last
XHQZ
TXD Clock High
T RXD Input Data Setup to TXD
DVXH
Clock High
T RXD Input Data Setup after TXD
XHDX
Clock High
NOTES
1 See Figure 13 for Waveforms
2 n is the value in the BxCMP register ignoring the ICLK bit
36
Parameter
1)
l
1)
e
1)
l
1)
e
1)
l
1)
e
1)
l
1)
e
value since the signal must pass through two 8259A
IRES
Min Max
T (n 1)
a
2T 35 2T
b
T 35 T
b a
(n 1) T 35 (n 1) T
b b b
T 35 T
b a
(n 1)T 35
b b
T 35
b
2T 35
b
T 35
b
T
a
T 20
a
0
Unit Notes
ns 1 2
35 ns 1
a
35 ns 1
35 ns 1 2
a
35 ns 1
ns 1 2
ns 1
ns 1
ns 1
20 ns 1
ns 1
ns 1