Clocks; Table 15. Multi-Bios Implementation - Intel 6 Series User Manual

Table 15. Multi-BIOS Implementation

Jumper
LED
3.2.12.2

Clocks

The development board supports both Integrated and Buffered clocking modes. By
default, the board's system clocks are provided by the CK505 (EU6V1) clock
synthesizer (Buffered mode).
The BCLK frequency can be set by stuffing/unstuffing the resistor pairs R6F25 and
R6F26, R6F27 and R6F22 and R6G1 and setting the jumper J6G1.
For the board, the default clock frequency must be 100 MHz and hence the required
configuration is to set the jumper J6G1 to 1-X.
CPUSTP# is not supported as this clock must always be running during buffered mode.
The clocks on the board are provided by the PCH, which uses clocks from CK505 as
inputs in Buffered-through mode. These inputs are used as a reference to generate all
the other platform clocks.
Overclocking is not supported during Buffered-through mode.
Fully integrated clocking mode: For FCIM, the CK505 can be unstuffed and PCH
provides all clocks. A general block diagram is shown in
2 nd Generation Intel ® Core™ Processor with Intel
User Guide
42
BIOS_SEL2 BIOS_SEL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
J9E3 J9E2
CR9E1 CR9E2
® 6 Series Chipset Development Kit
Development Kit Features
BIOS_SEL0 IMAGE
0 0 (DEFAULT)
1 1
0 2
1 3
0 4
1 5
0 6
1 7
J9E1
CR9E3
Figure 8.
Document Number: 325208-001
March 2011