Cisco MGX MGX 8800 Hardware Installation Manual page 558

PXM1E Specifications
Table A-3
Specification
Processor clock speed and memory
specifics
Maximum switch fabric throughput
Control access
Note
Number of logical ports
Alarm indicators (audible and visual)
BITS
Stratum 3 synchronization (internal and
external)
Cisco MGX 8800/8900 Series Hardware Installation Guide
A-4
PXM1E Specifications (continued)
These ports exist on the user
interface back cards.
2
clock interface
Description
Clock speed: 350 MHz internal, 100 MHz external
Flash memory: 2 MB
DRAM: 256 MB
Tertiary cache: 2 MB
External L3 cache: 2 MB
Secondary cache: 256 KB
1
BRAM : 512 KB
DRAM: 256 MB
Hard disk: 6 to 20 GB
CPU: R7000
1.2 Gbps
• Control port: RJ-45 receptacle, EIA/TIA-232, DTE
mode, asynchronous interface, 19,200 baud, 1 start
bit, 1 stop bit, no parity bits
Maintenance port: RJ-45 receptacle, EIA/TIA-232,
•
DTE mode, asynchronous interface, 19,200 baud, 1
start bit, 1 stop bit, no parity bits
LAN port: RJ-45 receptacle, 10BASE-T,
•
802.3 Ethernet
Two serial ports for the following:
•
PNNI modem port
–
IOS control port
–
IOS modem port
–
32 logical ports across all physical ports on the NNI/UNI
port back card (regardless of line type)
Central office-compatible alarm indicators and controls
through a DB-15 receptacle
T1 and E1 with an RJ-48 receptacle
Free-run accuracy of ± 4.6 ppm (± 7 Hz at 1.544 MHz)
•
• Holdover stability of less than 255 slips (± .37 ppm)
for the initial 24 hours of holdover
Upon clock switchover, MTIE
•
microsecond and rate of phase change does not
4
exceed 81 ns in a 1.326-ms interval
Pull-in range of accuracy ± 4.6 ppm
•
Provides jitter filtering and tolerance according to
•
AT&T T1.5 and ITU G.824 specifications
Declares a bad reference if LOS detected > 50 ms or
•
error burst of duration > 2.5 sec.
Releases 2 - 5.2, Part Number OL-4545-01, Rev. H0, May 2006
Appendix
3
does not exceed 1