Testable Type 4 Single-Beam Photoelectric Safety Switches - Mitsubishi MELSEC-WS0-CPU0 User Manual

Table 42:
Functions of testable Type 2
single-beam photoelectric
safety switches
Note
Table 43:
Connection of testable Type
4 single-beam photoelectric
safety switches
Note
Table 44:
Functions of testable Type 4
single-beam photoelectric
safety switches
Note
Connecting devices
Function
Testing Possible
Series connection/ SICK Wx12/18/24/27, Vx18:
cascading
 max. 2 pairs per input can be cascaded with test gap = 4 ms
 max. 5 pairs per input can be cascaded with test gap = 12 ms
SICK L21:
 max. 10 pairs per input can be cascaded with test gap = 4 ms
 max. 25 pairs per input can be cascaded with test gap = 8 ms
SICK L27/L28:
 max. 7 pairs per input can be cascaded with test gap = 4 ms
 max. 18 pairs per input can be cascaded with test gap = 12 ms
Take the max. line resistance of 100 Ω into account.
For further information refer to the manual of the testable Type 2 single-beam
photoelectric safety switches.
4.3.2

Testable Type 4 single-beam photoelectric safety switches

Electrical connection: Example from Setting and Monitoring Tool with WS0-XTIO
SICK L41
Use protected or separate cabling for the test output of the module (X1...X8) to the test
input of the transmitter and for the output of the receiver to the safe input of the
module (I1...I8). Otherwise a cross circuit between these signals can inhibit the error
detection by this test.
Function
Testing Necessary
Series connection/ SICK L41:
cascading
 max. 10 pairs per input can be cascaded with test gap = 4 ms
 max. 25 pairs per input can be cascaded with test gap = 8 ms
Take the max. line resistance of 100 Ω into account
For further information refer to the manual of the testable Type 4 single-beam
photoelectric safety switches.
(standard element)
(customized element required)
(standard element)
(customized element required)
(standard element)
(customized element required)
(standard element)
(customized element required)
Notes
Test input TE (transmitter) at X1
Output Q (receiver) at I1
Notes
Chapter 4
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