Usi: Data Receiving Timing Chart (Uart Mode); Usi: Data Transmission Timing Chart (Spi Mode) - Epson S1C33L26 Technical Manual

18 UNIVERSAL SERIAL INTERFACE (USI)
Sampling clock
USI_DI pin
start
(MSB first)
Shift register
RD[7:0]
URBSY
URDIF
Interrupt
18.5.2 Data Transfer in SPI Mode
Data transmission
To start data transmission in SPI mode, write the transmit data to the transmit data buffer (TD[7:0]/USI_TD
register).
The buffer data is sent to the transmit shift register. In SPI master mode, the module starts clock output from
the USI_CK pin. In SPI slave mode, the module awaits clock input from the USI_CK pin. The data in the shift
register is shifted in sequence at the clock rising or falling edge (see Figure 18.4.5.1) and sent from the USI_
DO pin.
The SPI controller includes two status flags for transfer control: STDIF/USI_SIF register and SSIF/USI_SIF
register.
The STDIF flag indicates the transmit data buffer status. STDIF is set to 1 indicating that the transmit data buf-
fer becomes empty when data written to the transmit data buffer is sent to the transmit shift register. STDIF is
an interrupt flag. An interrupt or DMA request can be generated when this flag is set to 1 (see Section 18.7).
Write subsequent data to the transmit data buffer to start the following transmission using this interrupt or
DMA. The transmit data buffer size is 1 byte, but a shift register is provided separately to allow data to be writ-
ten while the previous data is being sent. If an interrupt or DMA is not used for transmission, be sure to confirm
that the transmit data buffer is empty before writing transmit data. Writing data before STDIF has been set will
overwrite earlier transmit data inside the transmit data buffer.
In SPI master mode, the SSIF flag indicates the USI status. This flag switches to 1 when transmit data is written
to the transmit buffer and reverts to 0 after both the shift register and transmit buffer become empty. Read this
flag to check whether the SPI controller is operating or at standby.
spi_ck (master mode)
Write
TD[7:0]
Shift register
USI_CK pin
(SCPOL = 0, SCPHA = 1)
USI_CK pin
(SCPOL = 0, SCPHA = 0)
USI_DO pin
SSIF (master mode)
STDIF
Interrupt
Transmit buffer empty interrupt
18-8
A A parity stop start
D7 D0
Read
Receive buffer full interrupt
Figure 18. 5.1.2 Data Receiving Timing Chart (UART mode)
Write
Data A
A A A A A
D7 D6 D5 D4 D3
Reset by writing 1
Figure 18. 5.2.1 Data Transmission Timing Chart (SPI mode)
Seiko Epson Corporation
B B parity stop
D7 D0
Data A
Reset by writing 1
Receive buffer full interrupt
Data B
A A A B B
D2 D1 D0 D7 D6
Reset by writing 1
Transmit buffer empty interrupt
start C C parity stop
D7 D0
Data B
Overrun error interrupt
(when Data B has not been read)
B B B B B
D5 D4 D3 D2 D1
S1C33L26 TECHNICAL MANUAL
B
D0
(MSB first)