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13 SeRial inTeRFaCe
13.7
Data Transfer in SPi Mode
The serial interface supports serial data transfer in SPI mode.
This mode has the same serial master and slave functions and control method except that the SRDY output cannot
be used when P33 is configured to the SS terminal. Refer to Section 13.4, "Operating mode of serial interface," and
Section 13.6, "Data input/output and interrupt function," for these common descriptions.
SPi slave device
When using the S1C63004/008/016 as an SPI slave device, set the serial interface to SPI slave mode.
ESIF = "1," SMOD = "0," ENCS = "1," ESREADY = "0," ESOUT = "1" (when SOUT is used)
The P33 terminal functions as the SS (Slave Select) signal input terminal.
To perform data transfer in this mode, write "1" to SCTRG to enable the serial interface to transmit/receive data
the same as the slave mode described above. The serial interface starts data transfer when the external master
device outputs the synchronous clock to the SCLK terminal after it asserts the slave select signal (set to low) input
to the SS (P33) terminal. The external device must hold the SS signal (P33 terminal) active while data is being
transferred. When the SS signal is inactive, the serial interface does not start data transfer even if the synchronous
clock is input to the SCLK terminal.
SPi master device
When using the S1C63004/008/016 as an SPI master device, set the serial interface to master mode.
ESIF = "1," SMOD = "1," ENCS = "0," ESREADY = "0," ESOUT = "1" (when SOUT is used)
The SS signal output terminal is not available in master mode, set an I/O port to output mode and use it as the SS
signal output terminal. The SS signal must be set to low before writing "1" to SCTRG and hold that active level
while data is being transferred. After 8-bit data is transmitted/received, set the SS signal to high.
Timing chart
The data transfer timing chart in SPI mode is shown in Figure 13.7.1.
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SS input (Slave mode)
SS output (Master mode)
Figure 13.
Notes: • The S1C63004/008/016 serial interface does not have a transmit buffer and a receive buffer,
therefore, data transfer must be processed in every one-byte transfer. The interrupt factor flag
is set after a transfer for one byte has been completed. A start of data transfer from/to the SPI
device cannot be used as a trigger to start the interrupt handler.
• If the SS signal becomes inactive during data transfer in SPI slave mode or if the master device
outputs the SCLK signal before it asserts the SS signal, the serial interface cannot transmit/
receive data normally.
13-8
7.1 Timing chart in SPI mode (when SCPS1 = SCPS0 = "0")
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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