Evaluation Board Hardware; Typical Application Circuit - Analog Devices ADP1974-EVALZ User Manual

UG-883

EVALUATION BOARD HARDWARE

TYPICAL APPLICATION CIRCUIT

CENTRAL PC
Table 1. Input Pins that Require External Power Supplies or External Control Signals
Power Supply Connector
V 1 VIN
IN
V 1 EN
EN
V 1 MODE
MODE
V 2 FAULT
FAULT
V 3 COMP
COMP
V SYNC
SYNC
V can also be used to supply V
1
IN EN
2 When used with the AD8450, the FAULT signal is supplied by the FAULT pin (Pin 46) of the AD8450.
3 When used with the AD8450, the COMP signal is supplied by the VCTRL pin (Pin 59), the error amplifier output of the AD8450.
Table 2. Output Pins to Observe with Ammeter or Oscilloscope
Output
Signal Connector Signal
V 1 VREG 5 V dc
VREG
V DL 0 V to VREG square wave
DL
V DH 0 V to VREG square wave
DH
V SYNC 0 V to VREG square wave
SYNC
I CL Magnitude dependent
CL
on R
S
1 V provides the logic high signal for the MODE pin when a jumper is placed on the top two pins of the MODE test bus.
VREG
24V
VIN
VREG
MODE
FROM
EN
ADP1974
COMP
FROM
ANALOG IC
FAULT
FREQ
DMAX
GND
Figure 16.
Voltage Range (V) Purpose
6 to 60 Supplies power to the
0 to 60 Supplies logic signal to enable operation of the ADP1974.
0 to 5.5 Supplies logic signal to select boost/recycle mode or buck/charge mode.
0 to 60 Supplies the signal to indicate when a fault condition has occurred in the application
external to the ADP1974.
0.5 to 5.0 Supplies the error signal that is compared internally to the liner ramp to produce the
PWM signal.
0 to 5.5 Supplies the external synchronization waveform when the
and SYNC is configured as an input.
and V via jumper connections. Alternatively, EN and MODE can be powered with separate power supplies.
MODE
Recommended
Equipment
Ammeter or oscilloscope
Oscilloscope
Oscilloscope
Oscilloscope
Oscilloscope
triangle wave
SYNC
SCFG
DH
HV
MOSFET
DRIVER
DL
CL
DT
SS
ADP1974 Typical Application Circuit
ADP1974
Expected Measurement
When V
When MODE is logic low, a square wave is visible on DH.
When MODE is logic high, DL is complementary to DH.
When MODE is logic high, a square wave is visible on DL.
When MODE is logic low, DH is complementary to DL.
When SYNC is configured as an output, the SYNC pin outputs a
clock signal programmed by R
The current rises and falls with the duty cycle of DH and DL.
Rev. 0 | Page 8 of 12
ADP1974-EVALZ User Guide
24V RECYLCING
DC BUS
internal control circuitry.
ADP1974
> 6 V, V rises to 5 V.
IN VREG
.
FREQ
is a slave device,