Evaluation Board Hardware; Introduction To The Dc3252A; Accurately Measuring Output Ripple Of The Ltc3303A - Analog Devices LTC3303A User Manual

User Guide DC3252A

EVALUATION BOARD HARDWARE

INTRODUCTION TO THE DC3252A

The DC3252A demonstration circuit features the LTC3303A, a
low voltage synchronous step-down regulator. The LTC3303A is
a monolithic, constant frequency, current mode step-down DC-DC
converter. A 2 MHz oscillator turns on the internal top power switch
at the beginning of each clock cycle. Current in the inductor then
increases until the top switch comparator trips and turns off the top
power switch. If the EN pin is low, the LTC3303A is in shutdown
and in a low quiescent current state. When the EN pin is above its
threshold, the switching regulator is enabled.
The MODE/SYNC pin sets the switching mode to pulse skip, forced
continuous, or Burst Mode. If an external 1.6 MHz to 2.4 MHz clock
is connected to the MODE/SYNC turret while the JP1 is set to
Figure 13. V Ripple Without C9 X2Y Capacitor
the SKIP position, the LTC3303A switching frequency sync to the
OUT
external clock. The LTC3303A operates in forced continuous mode
while syncing. For more detailed information, refer to the LTC3303A
data sheet.
ACCURATELY MEASURING OUTPUT RIPPLE
OF THE LTC3303A
With the fast edge rates of the circuit, high frequency noise can
be observed when measuring the output voltage with 1 MΩ termi-
nated oscilloscope probes. To better view the output ripple with
oscilloscopes of 400 MHz bandwidth and above a 50 Ω coax cable
connected as close to the output caps as possible should be used
with the oscilloscope channel terminated to 50 Ω at the scope.
This helps to reduce the noise coupling onto and displaying on the
scope. The demo board is set up to solder an U.FL, RECEPT, ST
Figure 14. V Ripple with C9 X2Y Capacitor
SMD, 0 Hz to 6 GHz, 50 Ω connector (TP1) near the output cap
OUT
C6. These pads can also be used to solder a coax cable or other
oscilloscope probe connector if required.
The high frequency spikes are partially attributed to the inter-wind-
ing capacitance of the inductor and the voltage step is partially
attributed to the inductance in the output capacitors. This can
be reduced by choosing low ESL capacitors or adding small low
ESL capacitors in parallel to the output capacitors as close to the
inductor as possible. Figure 13 and Figure 14 show the output
ripple using a 500 MHz scope, 50 Ω probe with an added low ESL
X2Y capacitor added, C9, close to the inductor and GND return to
the input capacitors to reduce the inductance of the return path and
better filter the high frequency spikes.
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