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ADP1974-EVALZ User Guide
Maximum Duty Cycle Resistor (R
To customize the maximum duty cycle of the DH and DL pins
for the ADP1974, use Figure 14 to select R
450
T
= +25°C
A
400
350
300
250
200
150
100
50
0
0
20
40
DUTY CYCLE (%)
Figure 14. R
vs. Duty Cycle, R
DMAX
Current-Limit Set Resistor (R
If testing the current limit in an application, use the following
equation to set the current limit:
100
mV
(
)
mA =
I
PK
R
S
where:
I
is the desired peak current limit in mA.
PK
R
is the sense resistor used to set the peak current limit in Ω.
S
When the
ADP1974
is configured to operate in buck (charge)
mode, the internal current-limit threshold is set to 300 mV
(typical) and the negative valley current-limit threshold is set to
450 mV (typical). When the
in boost (recycle) mode, the internal current-limit threshold is
set to 500 mV (typical). The external resistor (R
offset the current properly to detect the peak in both buck and
boost operation. Set the R
CL
equations for setting the peak currents follow.
For buck/charge mode, the equations are
V
= (I
) × (R
) − (I
CL (BUCK)
CL
CL
V
= (I
) × (R
) + (I
NC (BUCK)
CL
CL
For boost/recycle mode, the equation is
V
= (I
) × (R
) + (I
CL (BOOST)
CL
CL
where:
V
= 300 mV typical.
CL (BUCK)
V
= 450 mV typical.
NC (BUCK)
V
= 500 mV typical.
CL (BOOST)
I
= peak inductor current.
PK
I
= valley inductor current.
VL(NEG)
I
= 20 µA, typical.
CL
R
= 20 kΩ.
CL
)
DMAX
.
DMAX
60
80
100
= 100 kΩ, V
= 5 V
FREQ
COMP
)
S
ADP1974
is configured to operate
) is needed to
CL
value to 20 kΩ. In operation, the
) × (R
)
PK
S
) × (R
)
VL(NEG)
S
) × (R
)
PK
S
The
ADP1974
is designed so that the peak current limit is the same
in both the buck mode and boost mode of operation. A tolerance
of 1% or better for the R
Soft Start Capacitor (C
The
ADP1974-EVALZ
evaluation board.
A C
capacitor is not required for the ADP1974. When the C
SS
capacitor is not used, the internal 5 µA (typical) current source
pulls the SS pin voltage to VREG, and there is no soft start control.
Use the following equation to calculate the delay time before
switching is enabled (t
0.52
=
t
REG
I
where:
I
= 5 µA, typical.
SS
C
= soft start capacitor value.
SS
During soft start, the
mode, and the synchronous FET is not driven. After the soft
start period is completed (SS > 4.5 V), the
full synchronous mode.
(6)
VOUT
VREG
4.5V
V
SS
0.52V
0V
APPLICATION SPECIFIC
When integrated in a battery test solution, the
controlled with external control signals from other devices in the
application. The FAULT pin allows an external device to signal
the
ADP1974
when an external fault occurs. The COMP pin
(7)
allows an external device to control the PWM output signals on
(8)
the DH and DL pins. The SYNC and SCFG pins can be used to
synchronize the
implement the
ADP1974
(9)
pins provide logic control to turn the
to transition the system between boost/recycle mode and
buck/charge mode.
Rev. 0 | Page 7 of 12
and R
resistors is recommended.
CL
S
)
SS
comes with a 1 nF capacitor on the
):
REG
×
C
SS
SS
ADP1974
operates in asynchronous
ADP1974
t
REG
SYNCHRONOUS
OPERATION
ENABLE
BEGIN
ADP1974
REGULATION
Figure 15. Soft Start Diagram
ADP1974
CONTROL
ADP1974
to an external clock signal or to
as a master clock. The EN and MODE
ADP1974
UG-883
SS
(10)
switches to
ADP1974
can be
on or off and
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