Adjusting The Adp1974-Evalz Components For A Specific Application - Analog Devices ADP1974-EVALZ User Manual

ADP1974-EVALZ User Guide
FAULT Test Point
Connect FAULT to VIN or apply an external voltage between 0 V
and 60 V. If SYNC is configured as an output, when V
(typical), a square wave is visible on the SYNC pin operating at
the frequency set by R .
FREQ
SYNC Test Point
If SYNC is configured as an output, connect an oscilloscope to
SYNC. The SYNC signal is visible when V
and V ≥ 1.2 V (typical).
FAULT
If SYNC is configured as an input, connect a signal with f
between 50 kHz and 300 kHz, with V
and V ≤ 1.05 V (typical).
SYNC(LOW)
COMP Test Point
Connect an external power supply to COMP. See Figure 8 for
the relationship between V
COMP
DH and DL.
100
T = 25°C
A
80
60
40
20
0
0.5 1.0 1.5 2.0
Figure 8. Duty Cycle vs. V , R
COMP FREQ
DL and DH Test Point
Connect the DH and DL pins to an oscilloscope. To observe a
signal on DH or DL, enable the
setting V ≥ 1.25 V (typical), V
EN
V ≥ 0.5 V (typical).
COMP
If V ≤ 1.05 V (typical), the
MODE
mode, and a square wave is visible on the DL pin. A
complementary square wave is visible on the DH pin.
≥ 1.2 V
FAULT
≥ 1.25 V (typical)
EN
SW
≥ 1.2 V (typical)
SYNC(HIGH)
and the switching duty cycle of
2.5 3.0 3.5 4.0 4.5 5.0
V (V)
COMP
= 100 kΩ, No Load on DL, DH, or DMAX
ADP1974 via the EN pin by
≥ 1.2 V (typical), and
FAULT
ADP1974 is in boost/recycle
COMP
INTERNAL RAMP
(4V p-p)
DH
DL
Figure 9. Signal Diagram for Boost Configuration
If V ≥ 1.20 V (typical), the
MODE
mode, and a square wave is visible on the DH pin. A
complementary square wave is visible on the DL pin.
COMP
INTERNAL RAMP
(4V p-p)
DH
DL
Figure 10. Signal Diagram for Buck Configuration
CL Test Point
Unless testing the current limit, connect CL to GND1 or GND2.
If testing the current, see the
mation about current limits and selecting R
ADJUSTING THE
FOR A SPECIFIC APPLICATION
For more detailed guidance in selecting the components to
customize the features of the ADP1974, consult the
data sheet.
Selecting R
FREQ
When V is ≥ 4.53 V, the
SCFG
When functioning as a master device, the
the frequency set by the external R
between FREQ and ground, and the
at the programmed frequency on the SYNC pin.
Rev. 0 | Page 5 of 12
BOOST MODE CONFIGURATION
MODE ≤ 1.05V (TYPICAL)
≥ 4.53V (TYPICAL)
V
SCFG
4.5V
2.5V
0.5V
0V
VREG (5V TYPICAL)
0V
VREG (5V TYPICAL)
0V
ADP1974 is in buck/charge
BUCK MODE CONFIGURATION
MODE ≥ 1.20V (TYPICAL)
≥ 4.53V (TYPICAL)
V
SCFG
4.5V
2.5V
0.5V
0V
VREG (5V TYPICAL)
0V
VREG (5V TYPICAL)
0V
ADP1974 data sheet for more infor-
to set the current limit.
S
ADP1974-EVALZ COMPONENTS
for a Master Device
ADP1974 operates as a master device.
ADP1974
resistor connected
FREQ
ADP1974
UG-883
ADP1974
operates at
outputs a clock