Evaluation Board Hardware; Device Description; Hardware Link Options - Analog Devices EVAL-AD7173-8SDZ User Manual

UG-631

EVALUATION BOARD HARDWARE

DEVICE DESCRIPTION

The AD7173-8 is a highly accurate, high resolution, multiplexed,
8-/16-channel (full/pseudo differential) Σ-Δ ADC. The
has a maximum channel-to-channel scan rate of 6.21 kSPS (161 µs)
for fully settled data The output data rates range from 1.25 SPS
to 31.25 kSPS. The device includes integrated analog input and
reference buffers, an integrated precision 2.5 V reference, and
an integrated oscillator.
See the AD7173-8 data sheet for complete specifications. Consult
the data sheet in conjunction with this user guide when using
the evaluation board. Full details for the
Analog Devices website.
Table 1. Default Link and Solder Link Options
Link Default Option
LK1 A
LK2 B
LK5 to LK20 Inserted
SL0 A
SL1 A
SL2 A
SL3 A
SL4 A
SL5 B
SL6 Removed
SL7 A
SL8 to SL9 A
SL10 A
SL11 A
SL12 to SL15 Inserted
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AD7173-8
SDP-B are available on the
Description
Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place in
Position A if using 5 V AVDD1, or Position B if using 2.5 V AVDD1.
Selects the external power supply from Connector J3 (Position A), or J4 (Position B).
Inserting these links sets up the on-board noise test. In this mode, all inputs short to the common
voltage via SL11.
Routes A0 to: AIN0/REF2− pin on the
single-ended to differential driver circuit (Position C), or J15-1 (Position D).
Routes A1 to: AIN1/REF2+ pin on the
single-ended to differential driver circuit (Position C), or J15-7 (Position D).
Routes A2 to: AIN2 pin on the AD7173-8
ended to differential driver circuit (Position C).
Routes A3 to: AIN3 pin on the AD7173-8
ended to differential driver circuit (Position C).
Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets
the AVDD2 voltage to 3.3 V supply from the
Selects between an external or on-board IOVDD source. Supplies IOVDD from the
(default). The evaluation board operates with a 3.3 V logic.
Position A connects Crystal Y1 as an external MCLK clock source. Position B connects MCLK SMA/SMB
connector for use as a clock input or an ADC internal clock output.
Selects between an external or on-board AVDD1 source. Supplies AVDD1 from the
(default).
Selects between a 5 V and 2.5 V LDO supply for AVDD1. Supplies AVDD1 with 5 V (default).
Selects the voltage applied to the AVDD1 pin. Operates using the supply set up by Link SL8 to Link SL9
(default). When inserted in Position B, sets the AVDD1 voltage to 3.3 V supply from the
regulator.
Selects the voltage applied to analog input during on-board noise test (LK5 to LK20 inserted). Position A
connects to the AD7173-8 REFOUT pin. Position B connects to GND. Position C connects to AVSS.
Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.
Rev. A | Page 4 of 34
EVAL-AD7173-8SDZ User Guide

HARDWARE LINK OPTIONS

See Table 1 for default link options. By default, the board is
configured to operate from the supplied 9 V ac-to-dc adapter
connected to Connector J4. The 5 V supply required for the
AD7173-8 comes from the on-board low dropout regulator
(LDO). The ADP1720, with a 5 V fixed output voltage, receives
its input voltage from J2 or J4 (depending on the position of
LK2) and generates a 5 V output.
AD7173-8 (Position A), Buffer U6 (Position B), U7 for use with a
AD7173-8 (Position A), Buffer U6 (Position B), U7 for use with a
(Position A), Buffer U10 (Position B), or U9 for use with a single-
(Position A), Buffer U10 (Position B), or U9 for use with a single-
ADP1720 (3.3 V) (U11) regulator.
ADP1720 (3.3 V) (U11)
ADP1720 (5 V) (U8)
ADP1720 (3.3 V)