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13.5 CHIPSET FEATURES SETUP
Option
BIOS
Default
Auto Configuration
En.
DRAM Timing
70 ns
DRAM RAS #
4
Precharge Time
DRAM R/W Leadoff
7/6
Timing
Fast RAS# to CAS#
3
Delay
DRAM Read Burst
x444/x
(EDO/FPM)
444
DRAM Write Burst
x444
Timing
Turbo Read Leadoff
Dis.
DRAM Speculative
Dis.
Leadoff
Turn-Around Insertion
Dis.
ISA Clock
PCI
CLK/4
System BIOS
Dis.
Cacheable
Video BIOS Cacheable
Dis.
8 Bit I/O Recovery
3
Time
16 Bit I/O Recovery
2
Time
Setup
Possible
Default
Settings
En.
En. ; Dis.
Auto Configuration selects predetermined optimal values of chipset
parameters. When Disabled, chipset parameters revert to setup
information stored in CMOS. Many fields in this screen are not
available when Auto Configuration is Enabled.
70ns
70 ns, 60ns
The value in this field depends on performance parameters of the
installed memory chips (DRAM). Do not change the value from the
factory setting unless you install new memory that has a different
performance rating than the original DRAMs.
4
4 ; 3
Select the number of CPU clocks allocated for the Row Address
Strobe (RAS # ) signal to accumulate its charge before the DRAM is
refreshed. If insufficient time is allowed, refresh may be incomplete
and data lost.
7/6
7/6 ; 6/5
Select the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Changing the
value from the setting determined by the board designer for the
installed DRAM may cause memory errors.
3
3 ; 2
When DRAM is refreshed, both rows and columns are addressed
separately. Use this item to determine the transition timing from RAS
to Column Address Strobe (CAS).
x444/x
x444/x444 ;
Sets the timing for reads from EDO (Extended Data Output) or FPM
444
x333/x444 ;
(Fast Page Mode) memory. The lower the timing numbers, the faster
x222/x333
the system addresses memory. Selecting timing numbers lower than
the installed DRAM is able to support can result in memory errors.
x444 ; x333 ;
Sets the timing for writes to memory. The lower the timing numbers,
x444
x222
the faster the system addresses memory. Selecting timing numbers
lower than the installed DRAM is able to support can result in
memory errors.
Dis.
En. ; Dis.
Select Enabled to shorten the leadoff cycles and optimize
performance in cacheless, 50-60 MHz, or one-bank EDO DRAM
systems.
Dis.
En. ; Dis.
A read request from the CPU to the DRAM controller includes the
memory address of the desired data. When Enabled, Speculative
Leadoff lets the DRAM controller pass the read command to memory
sightly before it has fully decoded the address, thus speeding up the
read process.
Dis.
En. ; Dis.
When Enabled, the chipset inserts one extra clock to the turn-around
of back-to-back DRAM cycles.
PCI
PCICLK/4 ;
You can set the speed of the AT bus at one-third or one-fourth of the
CLK/4
PCICLK/3
CPU clock speed.
En.
En., Dis.
Selecting Enabled allows caching of the system BIOS ROM at
E0000h-FFFFFh, resulting in better system performance. However,
if any program writes to this memory area, a system error may occur.
En.
En., Dis.
Selecting Enabled allows caching of the video BIOS ROM at C0000h
to C8FFFh, resulting in better video performance. However, in any
program writes to this memory area, a system error may occur.
1
1 ; 2 ; 3 ; 4 ; 5 ;
The I/O recovery mechanism adds bus clock cycles between PCI-
6 ; 7 ; 8 ; NA
originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus. These two fields let
you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
1
1 ; 2 ; 3 ; 4 ;
NA
13-7
BIOS Setups
Description
...
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