Table of Contents
Advertisement
PCI-934 Technical Reference Manual
CHIPSET FEATURES SETUP (Continued)
Option
BIOS
Default
Peer Concurrency
En.
Chipset Special
Dis.
Features
DRAM ECC/PARITY
Parity
Select
Memory Parity/ECC
Auto
Check
Single Bit Error Report
En.
L2 Cache Cacheable
64MB
Size
Chipset NA # Asserted
En.
Pipeline Cache Timing
Faster
Passive Release
En.
Delayed Transaction
Dis.
Memory Hole Location
None
Supervisor I/O Base
190h
Addr.
Setup
Possible
Default
Settings
En.
En. ; Dis.
Peer concurrency means that more than one PCI device can be
active at a time.
En.
En. ; Dis.
When Disabled, the chipset behaves as if it were the earlier Intel
82430FX chipset.
Parity
ECC ; Parity
Set this option according to the type of DRAM installed in your
system: error-correcting code (ECC) or parity (default).
Auto
En. ; Dis. ;
In Auto mode, the BIOS enables memory checking automatically
Auto
when it detects the presence of ECC or parity DRAM.
En.
En. ; Dis.
If ECC is enabled, selecting Enabled here tells the system to report
an error (NMI) when a correctable single-bit error occurs.
When disabled, a single-bit error will be corrected but not reported.
Use this option if your operating system does not support ECC error
scrubing.
64MB
64MB ; 512MB
Select 512MB only if your system RAM is greater than 64MB.
En.
En. ; Dis.
Selecting Enabled allows pipelining, in which the chipset signals the
CPU for a new memory address before all data transfers for the
current cycle are complete, resulting in faster performance.
Faster
Faster ;
For a secondary cache of 256KB (one bank), select Faster. For a
secondary cache of 512KB (two banks), select Fast (3-1-1-1, 2-1-1-
Fastest
1) or Fastest (3-1-1-1, 1-1-1-1). Cache timing 3-1-1-1 is at the CPU
access speed. It requires special SRAMs because the 3-1-1-1 timing
is at the CPU clock rate.
En.
En. ; Dis.
Select Enabled, to allow CPU to PCI bus accesses during passive
release otherwise the arbiter only accepts another PCI master
access to local DRAM.
Dis.
En. ; Dis.
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI version 2.1.
None
512K-640K ;
You can reserve this area of system memory for ISA adapter ROM.
15M-16M ;
When this area is reserved, it cannot be cached. The user
None
information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
190h
190h ; 290h ;
This parameter must reflect the jumper settings for TEKNOR I/O
390h
Base Port.
13-8
Description
Advertisement
Table of Contents
