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Installing and Working with System Components
6.4.2 POWER FAILURE DETECTION
A power failure may be detected if a low battery condition occurs (battery voltage drops
below 3V). The power failure detector status can be readout from one bit of the system
register located at the address 191h, 291h or 391h (depending on the I/O address selected in
CMOS setup).
This bit is described as follows:
x91 - Bit 0: PFO#, when goes low, indicates that a power failure condition .
For more information on system registers, please refer to Page 6-10
6.4.3 THERMAL MANAGEMENT
The thermal management is built around a digital temperature sensor and a thermal
watchdog. The device can be programmed to set its output when the temperature of the
processor exceeds a programmable high limit, and reset its output when the temperature is
under a programmable low limit. A special routine will throttle the CPU clock until the
temperature falls below the programmed low limit.
6.4.4 I/O REGISTER ADDRESSES
Three supervisor I/O registers (Register #1, Register #2, and Register #3) are provided to
configure and control special features of the board such as: watchdog control, RS-422/RS-
485 mode, and power fail output. These registers are two 8-bit registers which can be located
at three different I/O base addresses, 190h 290h or 390h.
When setting Register #1 at one base address (190h, 290h, or 390h), Register #2 and Register
#3 are located respectively at the Base Address plus one and Base Address plus two.
6-9
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