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PCI-934 Technical Reference Manual
Single-Stage Watchdog
In a single-stage configuration, the first watchdog detector monitors the output of the
first stage watchdog time-out.
To operate the watchdog, the processor drives the watchdog input (WDI) with an I/O
line. It toggles WDI once every 1.6 seconds (typical) to verify the proper software
execution. If a hardware or software failure occurs such that WDI is not toggled, the
watchdog output (WDO) will go low after 1.6 second, and reset the CPU. If the
processor can continue to run a 0-1-0 toggle routine, WDO will be set high by the next
transition of WDI.
In dual stage configuration, the WDO signal indicates the second stage watchdog when a
failure occurs. Following a reset, the watchdog is always disabled.
Dual Stage Watchdog
The dual-stage watchdog consists of a second watchdog in cascade with the first one: in
the event the first watchdog failed to toggle, the second stage is set.
Before the second stage watchdog resets the system, the first watchdog output can be tied
to the ISA's IOCHK line to generate an NMI to the CPU, while the two watchdog values
are stored. These values may be used to determine the cause of the system's reset.
CAUTION
The user program must provide the first access to address 190H (or
290H or 390H depending on the I/O address selected in CMOS setup),
and must also include the refresh routine.
Watchdog Flags
The watchdog status can be readout from two bits of the system register located at the
address 191h, 291h or 391h (depending on the I/O address selected in CMOS setup).
These bits are described as follows:
x91 - Bit 5: WDO, indicates that the last system reset was caused by a watchdog
timeout.
x91 - Bit 6: WDO1#, when goes low, indicates that the first level watchdog
timed out.
For more information on system registers, please refer to Page 6-10
6-8
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