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12.1.3 PANELLINK
The board provides a low voltage differential signal (LVDS) implemented through the
TM
PanelLink
technology. The major advantage of this high-speed interface is to enable a
flat panel display to be connected at up to 30 feet from the board using a 3 data pairs and a
clock pair cable.
The onboard Panel Link interface may be represented as follows:
PanelLink
Transmitter
Data
24
DE
Video
Controller
Ctrl
6
Clk
PCI-934 SBC
§
Characteristics
The Panel Link is capable of supporting true colors XGA Active Matrix Liquid Crystal
Display panels. DSTN with VGA and SVGA resolutions is also possible.
The transmitter takes parallel video/graphics data from the video controller and
transmits it serially to a PanelLink receiver at 195MB/sec.
Full color (up to 16.7M colors/pixel for 640x480 and 800x600 resolutions), high-
resolution (64K colors for 1024x768 resolution) Active matrix liquid crystal displays
at 65MHz pixel clock are supported.
§
Connection
Connecting a flat panel through the Panel Link connector (J2) requires a Panel Link
receiver interface. This interface decodes the serial data and transmit it in parallel to
the flat panel, through an 8-pair cable and a 20-pin dual-row female header at one end,
and an adequate connectors at the other end for the flat panel display connection.
The cable length is 6 feet with twisted flat cable, and can be increase to 30 feet using
high performance individually shielded-pair cable.
§
Settings
The amplitude of the differential signal is adjusted using the BIOS setup program
(BIOS Feature Setup – PanelLink Adjustment option). Higher amplitude provides a
better noise immunity but generates more EMI.
The parameter (0-15) should be adjusted to the smallest acceptable value.
TM
INTERFACE
Data 3 pairs
J2
Clock 1 pairs
12-7
Exploring the Multimedia Capabilities of the Board
PanelLink
Receiver
Data
24
DE
Ctrl
6
Clk
Flat Panel Display
LCD Display
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