Chipset Features Setup - Teknor Industrial Computers VIPer 821 Technical Reference Manual

VIPer 821 - Technical Reference Manual
4.4

CHIPSET FEATURES SETUP

Option BIOS
Default
Auto Configuration En.
DRAM Timing 70ns
DRAM RAS#
Precharge Time
DRAM R/W Leadoff
Timing
Fast RAS# to CAS#
Delay
x333/ x444 x333/ x444
DRAM Read Burst
(EDO/FPM)
DRAM Write Burst x333
Timing
Turbo Read Leadoff Dis.
DRAM Speculative Dis.
Leadoff
Turn-Around Insertion Dis.
PCI CLK/ 4
ISA Clock
System BIOS Dis.
Cacheable
Video BIOS Dis.
Cacheable
8 Bit I/O Recovery
Time
16 Bit I/O Receiving
Time
Setup Possible
Default Settings
En. En., Dis.
70ns 70ns, 60ns
4 4 4, 3
7/6 7/6 7/6, 6/5
3 3 3, 2
x444/ x444,
x333/ x444,
x222/ x333
x333 x444, x333,
x222
Dis. En., Dis.
Dis. En., Dis.
Dis. En., Dis.
PCI CLK/ 4
PCI CLK/ 4,
PCI CLK/ 3
En. En., Dis.
En. En., Dis.
3 1 1-8, NA
2 1 1-4, NA
Description
Auto Configuration selects predetermined optimal values of
chipset parameters. When Disabled, chipset parameters revert to
setup information stored in CMOS. Many fields in this screen are
not available when Auto Configuration is Enabled.
The value in this field depends on performance parameters of the
installed memory chips (DRAM). Do not change the value from
the factory setting unless you install new memory that has a
different performance rating than the original DRAMs.
Select the number of CPU clocks allocated for the Row Address
Strobe (RAS#) signal to accumulate its charge before the DRAM
is refreshed. If insufficient time is allowed, refresh may be
incomplete and data lost.
Select the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Changing
the value from the setting determined by the board designer for
the installed DRAM may cause memory errors.
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of
the transition from RAS to Column Address Strobe (CAS).
Sets the timing for reads from EDO (Extended Data Output) or
FPM (Fast Page Mode) memory. The lower the numbers, the
faster the system addresses memory. Selecting timing numbers
lower than the installed DRAM is able to support can result in
memory errors.
Sets the timing for writes to memory. The lower the timing
numbers, the faster the system addresses memory. Selecting
timing numbers lower than the installed DRAM is able to support
can result in memory errors.
Select Enabled to shorten the leadoff cycles and optimize
performance in cacheless, 50-60 MHz, or one-bank EDO DRAM
systems.
A read request from the CPU to the DRAM controller includes the
memory address of the desired data. When Enabled, Speculative
Leadoff lets the DRAM controller pass the read command to
memory sightly before it has fully decoded the address, thus
speeding up the read process.
When Enabled, the chipset inserts one extra clock to the turn-
around of back-to-back DRAM cycles.
You can set the speed of the AT bus at one-third or one-fourth of
the PCI clock speed (60 or 66 MHz).
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting
However, if any program writes to this memory area, a system
error may occur.
Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance.
However, in any program writes to this memory area, a system
error may occur.
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for
16-bit and 8-bit I/O.
4-6
in better system performance.