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Intel SBC 711 Hardware Reference Manual
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Intel SBC 711 Hardware Reference Manual

Intel SBC 711 Hardware Reference Manual

Analog input board .
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SBC 711
.
ANALOG INPUT BOARD
HARDWARE REFERENCE MANUAL
•
Manual
Order Number:
9800485A
Copyright
1977
I
I
Intel Corporation,
3065 Bowers
Avenue,
Santa
Clara, California 95051

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Summary of Contents for Intel SBC 711

  • Page 1 SBC 711 ANALOG INPUT BOARD HARDWARE REFERENCE MANUAL • Manual Order Number: 9800485A Copyright 1977 Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051...
  • Page 3 PREFACE Intel MULTIBUS Inter- facing,...
  • Page 4 CONTENTS CHAPTER 1 CHAPTER 4 PRINCIPLES OF OPERATION Page GENERAL INFORM ATION Page Introduction ... Introduction ....Description.
  • Page 5 TABLES ILLUSTRATIONS Figure Title...
  • Page 7 CHAPTER G_E_N_E_R_A_L_IN_F_O_R_M_A_T_IO_N_ 1·1. INTRODUfTION 1·2. DESCRIPrlON %fC.
  • Page 8 (Sill) amplifier. The ADC jumper-selected for + JOV, The following are supplied with the SBC 711 Analog Input ± 5V, and ± JOV full-scale inputs. The AID conversion pro- board: cess can be initiated by an external trigger,...
  • Page 11 CHAPTER 2 PREPARATION FOR USE...
  • Page 12 PIN* SIGNAL FUNCTION PIN* SIGNAL FUNCTION ADRF! Ground ADRC! +5 VDC ADRD! +5 VDC ADRAI Power input +5 VDC ADRB! +5 VDC ADR8! ADR9! Address bus ADR6! ADR7! ADR4! ADR5! Ground ADR2! ADR3! INIT! System Initialize ADRO! ADRI/ MRDC! Memory Read Command MWTC! Memory...
  • Page 13 Address. Constant Clock. Data. Initialize. Inhibit RAM. Inhibit ROM. Interrupt. Memory Read Commond. Memory Write Commond. XACK! Transfer Acknowledge.
  • Page 14 SIGNALS MIN. MAX. UNITS SYMBOL PARAMETER DESCRIPTION TEST CONDITIONS ADRO/-ADRF/ Input Low Voltage MRDC/ Input High Voltage -0.4 MWTC/ Input Current at Low V p.,A Input Current at High V Capacitive Load XACK! Output Low Voltage 32 mA Output High Voltage -5.2 p.,A Output Leakage High...
  • Page 15 twCMD l--tAS 'XACK ADDRESS MWTCI XACKI f--tDS DATAl VALID DATA WRITE TO REGISTER AOORES~ _____X t_Ac_C VA_L_ID_DA_T_A_--I ••• 2-2A...
  • Page 16 16 single-ended or 8 differential input channels Straight Binary Code *66-67 as described in paragraph 2-16. SBC 711 is shipped with jumpers configured single-ended channel operation Offset Binary Code (2's Complement) 67-70 shown in figure 2-3A.
  • Page 17 both ~" ~" 2-14. TRANSFER ACKNOWLEDGE DELAY (XACK!) XACK! G" 976.6 f.tsec...
  • Page 18 73 and 76 to terminal INT2I jumper terminals 72 and 77 to termina175. (Refer to table 2-10.) INn/ MULTIBUS INT4/ INT5/ INT6/ The SBC 711 includes dc-to-dc converter module (M5) INTI/ which supplies 15V and -15V power at 150 mA analog circuits.
  • Page 19 2-16. MULTIPLEXER CHANNEL EXPANSION ± %...
  • Page 20 2-15. Figures 2-5 and 2-6 illustrate methods of connecting single- NOTES: ended and differential voltage sources to the SBC 711 inputs. Refer to figure 5-1. R 15 through R22 are located in zone Figure 2-7 shows single-ended sources connected as differ- D5;...
  • Page 21 N0' U i r--T-- OVERAll CABLE SHIElO ~-SBC; T.P. S.E. CH 0 I )1 T.P. S.E. CH 1 • T.P. HI" S.E. CH 15 E em SYSTEM RACK 487-7...
  • Page 22 - -- I>: • "'0 "- "-...
  • Page 23 r -- - - - - DIFF CH 0 D1FF CH 1 • DIFF CH 7 E em SYSTEM RACK IMPORT...
  • Page 25 CHAPTER 3 PROGRAMMING INFORMATION noo; CHANNEL SELECT (1 of n05.
  • Page 26 Write to M+ the MUX address and gain may be verified cessors are sharing the SBC 711 and require a "semaphore." by performing a Read of M Note that the Board Busy bit can be cleared only by Write Com- mand to M+O with bit 3 clear.
  • Page 27 3-11. PROGRA~MING EXAMPLES BIT 11...
  • Page 28 PUBLIC RANCHN ;READ RANDOM CHANNEL. PUBLIC RPSClIN ;REPETITIVE SINGLE CHANNEL, INTERRUPT. PUBLIC SCAN ;SEQUENTIAL CHANNEL, NON-INTERRUPT. PUBLIC SEQCHN ;SEQUENTIAL CHANNEL, INTERRUPT. BASE 0F700H ;BASE ADDRESS OF INTERFACE. ;A/D COl'II1AND REG ISTEIl.. BASE+0 EQ.U STAT BASE+0 ;A/D STATUS REGISTER. BASE+l ;GAIN, I1UX ADDRESS REGISTER. EQ1J BASE+2 ;LAST CHANNEL REGISTER(WRITE...
  • Page 29 ;***************************************************************** ;***i********************************************************* ;***************************************************************** CSF.G {'UGH xenc LHLD :N,D ;***************************************************************...
  • Page 30 CSEG RANCHN: H,FCR ;POINT HL TO FIRST CHANNEL REGISTER. GAIN ;LOAD GAIN. l'IOV FSTCHN ;LOAD CHANNEL. ;ADD GAIN BITS. 1'IOV ; LOAD FIRST CHANNEL REGISTER. ;POINT TO COMMAND/STATUS REGISTER. l'IV M,GO ; START CONVERS ION • RANI: PIOV ; READ STATUS. IU,C ;CIlliCK EOC STATUS.
  • Page 31 lImv ;************************************************************ t~§,EG 1811:6 H,LeR LSTC:an ;LOAD LAST CHANNEL. ;****~************************************************************ FSTCHN ;LOAD CITANNEL • ;ADD GAIN BITS. !'I,A pomT REGISTEH. rrlTEUltUPT8.
  • Page 33 CHAPTER 4 PRINCIPLES OF OPERATION FUNCTldNAL DESCRIPTION...
  • Page 34 1/ a~d iNH2/ are generated from the No detailed discussion is included for the ADC and DC- address on the Multibus, the only way the SBC 711 can control mOdules1 These modules are replaceable as a unit part. pulse width of INH1/ and INH2/ is by delaying the XACK! 4-10.
  • Page 35 LTJ L J LTJ (AUX PWR) CONTROL DATA ADDRESS...
  • Page 37 RCR! WCR! gtted WCR! WCR! word WCR! RCR!
  • Page 38 A12-13 via A20-1. plied to the input of S/H amplifier module. If the present controller is finished with the SBC 711, a Write The Write Command to 1 has now (1) selected the proper Command to M+O with and all...
  • Page 39 must 14T,...
  • Page 40 If the present controller is finished with the SBC 711, a Write by a Write Command to M+3 with bits 4 and 5 clear. Command to M+O with and all zeros word disables the inter- WINT/ signal from decoder A15 and IDT4 bit inhibit A20-10 rupts;...
  • Page 41 CHAPTER 5 SERVICE INFORMATION CALlBRfTION <...
  • Page 42 MCD Technical Support Center before graph 2-17. Voltage source must be capable of supplying returning a product to Intel for service or repair. You will be 20 mA. given a "Repair Authorization Number" , shipping instructions, and other important information which...
  • Page 43 NOTES: FOR SCHEMATIC SEE D2001397. DOT IDCATES PIN I OF LC.'S AND M4. TERMINALS TO BE MACHtlE INSERTED BEFORE OTHER COMPONENTS. ASSEMELE tl ACCORDANCE WITH A2-I027. MAX. COMPCNENT HIGHT 0.475~ CAUTION, CMOS SEE HANDlNG PROCEDURE.
  • Page 45 REQUIRED. flI26 BUS 1~04~04 141504 "19 14LS,2 L-2p 74132 74lS00 '141'2 NOTE:USER WIRE INTERRUPTS R" •..• -J+5V ~ ~~~ ~1t intel' 14.J JOIIIOWtlI1 AVI. """ """ ,~[~I~ ~ ~ ," ANALOG "";;-- •• 0 I 2001397 lOf2 ICAU: IN[[T Tm.t...
  • Page 47 INCH105B lNCH9 '_~.I - '. INCHa3B!~ RAoeW lNCH7 INCH6 INCH5 IN CH4 INCH3~_1 INCH2 "d ~ ARE OPTIONAL, CUSTO~R INSTALLED. "TV ""*f-- ,r¥.=1- " :;::::. ." 1'1' intel' 15Uf tllTE:: DOTTED LINES 1f'()ICATE FACTORY STRAPPED CONFIGURATION. ""' " " LA"''''...
  • Page 49 APPENDIX __________ C_A_L_IB_R_A_T_IO_N_P_R_O_G_R_A_M_ F700 PUBLIC PGAADJ ;PGA ADJUSn7ENT. PUBLIC ADCOFF ;ADC OFFSET ADJUSTMENT. PUBLIC ADCRNG ;ADC RANGE ADJUSTMENT. PUBLIC RANCHN ;READ RANDOM CHANNEL. BASE 0F700H ;BASE ADDRESS OF INTERF ACE. BASE+O ;A/D CO.HMAND REGISTER. STAT BASE+0 ;A/D STATUS REGISTER. BASE+I ;GAIN.
  • Page 50 ;SET GAIN A,'XI GAIN ADCI: H,BUF TO BUFI<'ER. BUFFER PO I NTER FOR 'RArfCHN' • SHLD DATPT CALL RANCHN ; CCNVERT CHANNl~L 0 • ; PO IN TO PO INTER. H,BUF ; POINT TO lIISBYTE. !"iOV ;LOAD N.'mYTE. ; DISPLAY lIISBYTE ON CONSOLE.
  • Page 51 QSEG DBITE: PUSH ;SAVE REG. C. ;LOAD DATA. ;SWAP LOW NIBBLE HIGH NIBBLE. ;WITH ~ALL HXl\SC ;DISPLAY RESULT ON CONSOLE. CALL ;LOAD EXTRA COPY OF DATA. (::ALL HXASC CONVERT LOW NIBBLE TO ASC I ~ALL ;DISPLAY LOW NIBBLE ON CONSOLE. ;EXIT DBYTE.