Advanced Chipset Features - AXIOMTEK SBC82810 Series User Manual

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SBC82810 Pentium M All-in-One Half-Size Board User's Manual
4.7

Advanced Chipset Features

Since the features in this section are related to the chipset on
the CPU board and are completely optimized, you are not
recommended to change the default settings in this setup table
unless you are well oriented with the chipset features.
CMOS Setup Utility-Copyright © 1984-2001 Award Software
Advanced Chipset Features
DRAM Timing
CASs Latency Time
Active to Recharge Delay
DRAM RAS# to CAS# Delay
DRAM RAS# Recharge
DRAM Data Integrity Mode
MGM Core Frequency
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
Delayed Transaction
Delay Prior to Thermal
AGP Aperture Size (MB)
Init Display First
** On-Chip VGA Setting **
On-Chip VGA
On-Chip Frame Buffer Size
Boot Display
Panel Scaling
Panel Number
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
SDRAM CAS latency Time
You can select CAS latency time in HCLKs 2, 3, or Auto. The
board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless
you change specifications of the installed DRAM or the installed
CPU.
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in
the system. The default setting is "Non-ECC".
42
By SPD
2.5
7
3
3
Non-ECC
Auto Max 400/333MHz
Enable
Disabled
Disabled
Disabled
16 Min
64
Onboard
Enabled
32MB
Auto
Auto
640 x480
Award BIOS Utility
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