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3 – 2
3.1 Input Stage
3.2 Output Stage
3.3 Overload Detection
The input is terminated into 50 Ω by the parallel combination of R100
& R101. The input signal is coupled via a 47 Ω resistor to the high
speed "clamp-amp," U100. U100 is configured as a non-inverting
gain 2 amplifier. Pins 8 & 5 on U100 define input clamping thresh-
olds of
0.31 V. If the input signal exceeds these thresholds then
U100 will use the clamping thresholds as inputs, thereby limiting
the output to
0.62 V. This prevents the output of U100 from over-
driving the next gain stage.
Input signals in excess of 1.4 V are shunted to ground via the input
protection diodes D100 & D101. Normally both the diodes in D100
are reversed biased and so they do not interfere with the signal. The
diodes in D101 are forward biased by R103 & R104. When the input
signal exceeds
1.4 V (7
D100 will begin to conduct, thereby limiting the input to U100 to a
safe level.
The gain of U100 can be adjusted by
brated at the factory to set the overall gain of the channel to 5 when
terminated into a 50 Ω load. The output of U100 is passed to the next
gain stage via R112, a 47 Ω resistor.
The next stage has a fixed gain of 5
adjustable high frequency response. The gain of U101 is set by R115
& R116. The offset, adjusted by P101 and injected by R117, is nulled
at the factory. The high frequency response of U101 is affected by
the source impedance of its input signal and its feedback network.
Turning P102 clockwise decreases the source impedance of the feed-
back signal and increases the high frequency response of the gain
stage. P102 is adjusted at the factory for an optimum pulse response
providing a typical 3dB bandwidth of 350 MHz.
The output from U101 is passed to the front-panel output BNC
via the parallel resistors R118 & R119, providing a 50 Ω output
impedance. These resistors, in combination with the 50 Ω load re-
sistor (provided by the user), attenuate the signal by 2
overall gain is 5 .
Overloads are detected at the output of the second gain stage, U101.
A positive overload is rectified by D102 and charges C107. A nega-
tive overload is rectified by D102 and discharges C106. One of the
Circuit Description
the full scale input), one of the diodes in
10 % by P100, which is cali-
with an adjustable offset and
SIM914 350 MHz Preamplifier
so that the
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