Dram Clock; Dram Timing; Bank Interleave - Acorp 7KT266A User Manual

Chapter 2 Chapter 2
Chapter 2 Chapter 2 Chapter 2

DRAM Clock

This item determines DRAM Clock following the CPU
host clock.
The Choices: By SPD(default), 100, 133.

DRAM Timing

The DRAM timing is controlled by the DRAM Timing
Registers. The Timings programmed into this register are
dependent on the system design.
The Choices: By SPD(default), Manual.
SDRAM CAS Latency
2.5 (default)
3

Bank Interleave

The Choices: Disabled(default), Enabled.
Active to Precharge
7T
6T (default)
5T
DRAM Command Rate
The Choices: 2T Command(default), 1T Command.
CMOS Setup Utility-Copyright (C) 1984-2001 Award Software
AGP & P2P Bridge Control
AGP Aperture Size
AGP Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
AGP Master 1WS Write
AGP Master 1WS Read
←→↑↓: Move
Enter:Select
F1:General Help F5:Previous Values
F7:Optimized Defaults
Set SDRAM latency Time to
2.5.
Set SDRAM latency Time to 3.
Set DRAM Precharge in 7.
Set DRAM Precharge in 6.
Set DRAM Precharge in 5.
128M Item Help
4X
Auto Menu Level
DA
Disabled
Disabled
Disabled
+/-/PU/PD:Value F10:Save ESC:Exit
F6:Fail-Safe Defaults
2-15 2-15 2-15
2-15 2-15
BIOS Setup BIOS Setup
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