Advanced Chipset Features; Dram Clock / Drive Control - Acorp 7KT333 User Manual

Bhapter 1 Bhapter 1
Bhapter 1 Bhapter 1 Bhapter 1

2.4 Advanced Chipset Features

This section allows you to configure the system based on
the specific features of the installed chipset. This chipset
manages bus speeds and access to system memory resources,
such as DRAM and external cache. It also coordinates
communications of the PCI bus. It must be stated that these
items should never need to be altered. The default settings
have been chosen because they provide the best operating
conditions for your system. The only time you might
consider making any changes would be if you discovered that
data was lost while using your system.
◎ ◎ ◎ ◎ ◎ Figure 4. Advanced Chipset Features
CMOS Setup Utility-Copyright(C) 1984-2001 Award Software

DRAM Clock / Drive Control

AGP & P2P Bridge Control
CPU & PCI Bus Control
Chipset Register Adjust
Memory Hole
System BIOS Cacheable
Video RAM Cacheable
←→↑↓: Move
F1:General Help
F7:Optimized Defaults
CMOS Setup Utility-Copyright (C) 1984-2001 Award Software
Current FSB Frequency
Current DRAM Frequency
DRAM Clock
DRAM Timing
*SDRAM CAS Latency
*Bank Interleave
*Precharge to Active(Trp)
*Active to Precharge(Tras)
*Active to CMD(Trcd)
*DRAM Queue Depth
DRAM Command Rate
←→↑↓: Move
F1:General Help
F7:Optimized Defaults
Advanced Chipset Features
Enter:Select +/-/PU/PD:Value
F5:Previous Values
DRAM Clock / Drive Control
Enter:Select +/-/PU/PD:Value
F5:Previous Values
1 - 1 4 1 - 1 4 1 - 1 4
1 - 1 4 1 - 1 4
Press Enter Item Help
Press Enter
Press Enter Menu Level
Press Enter
Disabled
Disabled
Disabled
F10:Save ESC:Exit
F6:Fail-Safe Defaults
133MHz Item Help
166MHz
By SPD Menu Level
By SPD
2.5
Disabled
3 T
6 T
3 T
4 Level
2T Command
F10:Save ESC:Exit
F6:Fail-Safe Defaults
BIOS Settp BIOS Settp
BIOS Settp BIOS Settp BIOS Settp