Dram Clock; Dram Timing; Sdram Cas Latency; Bank Interleave - Acorp 4PM266M User Manual

Bhapter 1 Bhapter 1
Bhapter 1 Bhapter 1 Bhapter 1
CMOS Setup Utility-Copyright (C) 1984-2001 Award Software
Current FSB Frequency
Current DRAM Frequency

DRAM Clock

DRAM Timing

*SDRAM CAS Latency

*Bank Interleave

*Precharge to Active(Trp)
*Active to Precharge(Tras)
*Active to CMD(Trcd)
DRAM Command Rate
CPU Read DRAM Mode
←→↑↓: Move
F1:General Help
F7:Optimized Defaults
DRAM Clock
This item determines DRAM Clock following the CPU
host clock.
The Choices: By SPD(default), 100, 133.
DRAM Timing
The DRAM timing is controlled by the DRAM Timing
Registers. The Timings programmed into this register are
dependent on the system design.
The Choices: By SPD(default), Manual.
SDRAM CAS Latency
2 (default)
3
Bank Interleave
The Choices: Disabled(default), Enabled.
Active to Precharge
7T
6T (default)
5T
DRAM Clock / Drive Control
Enter:Select +/-/PU/PD:Value
F5:Previous Values
1 - 1 5 1 - 1 5 1 - 1 5 1 - 1 5 1 - 1 5
Item Help
By SPD Menu Level
By SPD
2
Disabled
3 T
6 T
3 T
2T Command
Medium
F10:Save ESC:Exit
F6:Fail-Safe Defaults
Set SDRAM latency Time to 2.
Set SDRAM latency Time to 3.
Set DRAM Precharge in 7.
Set DRAM Precharge in 6.
Set DRAM Precharge in 5.
BIOS Settp BIOS Settp
BIOS Settp BIOS Settp BIOS Settp